spi: rspi: Increase bit rate accuracy on RZ/A

rspi_rz_set_config_register() favors high values of "brdv" over high
values of "spbr".  As "brdv" is not a plain divider, but controls a
power-of-two divider, this may cause the selection of non-optimal
divider values.  E.g. on RSK+RZA1, when 3.8 MHz is requested, the actual
configured bit rate is 2.08 MHz (spbr = 1, brdv = 3), while 3.7 MHz
would be possible (spbr = 8, brdv = 0).

Fix this by only resorting to higher "brdv" values when really needed.
This makes the driver always pick optimal divider values on RZ/A.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20200819125904.20938-4-geert+renesas@glider.be
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
index 450a42ec2141a89585c8c5124f2aa36f9c457d9f..ad4ac867170b101a26b0a70015ba5f2ec30969c2 100644 (file)
--- a/drivers/spi/spi-rspi.c
+++ b/drivers/spi/spi-rspi.c
@@ -298,15 +298,13 @@ static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
        rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
 
        clksrc = clk_get_rate(rspi->clk);
-       while (brdv < 3) {
-               if (rspi->speed_hz >= clksrc/4) /* 4=(CLK/2)/2 */
-                       break;
+       spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1;
+       while (spbr > 255 && brdv < 3) {
                brdv++;
-               clksrc /= 2;
+               spbr = DIV_ROUND_UP(spbr + 1, 2) - 1;
        }
 
        /* Sets transfer bit rate */
-       spbr = DIV_ROUND_UP(clksrc, 2 * rspi->speed_hz) - 1;
        rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
        rspi->spcmd |= SPCMD_BRDV(brdv);