drm/amd/powerplay: set SOCCLK DPM for sienna_cichlid

Support for SOCCLK DPM for sienna_cichlid.
Use feature mask to control DPM for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 4aa1741..4a60b68 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -42,7 +42,8 @@
 #define FEATURE_MASK(feature) (1ULL << feature)
 #define SMC_DPM_FEATURE ( \
        FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
-       FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))
+       FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
+       FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))
 
 #define MSG_MAP(msg, index) \
        [SMU_MSG_##msg] = {1, (index)}
@@ -259,13 +260,20 @@ static int
 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
                                  uint32_t *feature_mask, uint32_t num)
 {
+       struct amdgpu_device *adev = smu->adev;
+
        if (num > 2)
                return -EINVAL;
 
        memset(feature_mask, 0, sizeof(uint32_t) * num);
 
-       *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
-                               | FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
+       *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT);
+
+       if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
+               *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
+
+       if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
+               *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 
        return 0;
 }