Merge branches 'clk-typo', 'clk-json-schema', 'clk-mtk-2712-eco' and 'clk-rockchip...

 - Convert a few clk bindings to JSON schema format
 - 3rd ECO fix for Mediatek MT2712 SoCs

* clk-typo:
  clk: samsung: fix typo

* clk-json-schema:
  dt-bindings: clock: Convert fixed-factor-clock to json-schema
  dt-bindings: clock: Convert fixed-clock binding to json-schema

* clk-mtk-2712-eco:
  clk: mediatek: update clock driver of MT2712
  dt-bindings: clock: add clock for MT2712

* clk-rockchip:
  clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks
  clk: rockchip: fix frac settings of GPLL clock for rk3328

diff --git a/Documentation/devicetree/bindings/clock/fixed-clock.txt b/Documentation/devicetree/bindings/clock/fixed-clock.txt
deleted file mode 100644 (file)
index 0641a66..0000000
--- a/Documentation/devicetree/bindings/clock/fixed-clock.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Binding for simple fixed-rate clock sources.
-
-This binding uses the common clock binding[1].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible : shall be "fixed-clock".
-- #clock-cells : from common clock binding; shall be set to 0.
-- clock-frequency : frequency of clock in Hz. Should be a single cell.
-
-Optional properties:
-- clock-accuracy : accuracy of clock in ppb (parts per billion).
-                  Should be a single cell.
-- clock-output-names : From common clock binding.
-
-Example:
-       clock {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <1000000000>;
-               clock-accuracy = <100>;
-       };

diff --git a/Documentation/devicetree/bindings/clock/fixed-clock.yaml b/Documentation/devicetree/bindings/clock/fixed-clock.yaml
new file mode 100644 (file)
index 0000000..b657ecd
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fixed-clock.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/fixed-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Binding for simple fixed-rate clock sources
+
+maintainers:
+  - Michael Turquette <mturquette@baylibre.com>
+  - Stephen Boyd <sboyd@kernel.org>
+
+properties:
+  compatible:
+    const: fixed-clock
+
+  "#clock-cells":
+    const: 0
+
+  clock-frequency: true
+
+  clock-accuracy:
+    description: accuracy of clock in ppb (parts per billion).
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  clock-output-names:
+    maxItems: 1
+
+required:
+  - compatible
+  - "#clock-cells"
+  - clock-frequency
+
+additionalProperties: false
+
+examples:
+  - |
+    clock {
+      compatible = "fixed-clock";
+      #clock-cells = <0>;
+      clock-frequency = <1000000000>;
+      clock-accuracy = <100>;
+    };
+...

diff --git a/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt b/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt
deleted file mode 100644 (file)
index 189467a..0000000
--- a/Documentation/devicetree/bindings/clock/fixed-factor-clock.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-Binding for simple fixed factor rate clock sources.
-
-This binding uses the common clock binding[1].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible : shall be "fixed-factor-clock".
-- #clock-cells : from common clock binding; shall be set to 0.
-- clock-div: fixed divider.
-- clock-mult: fixed multiplier.
-- clocks: parent clock.
-
-Optional properties:
-- clock-output-names : From common clock binding.
-
-Some clocks that require special treatments are also handled by that
-driver, with the compatibles:
-  - allwinner,sun4i-a10-pll3-2x-clk
-
-Example:
-       clock {
-               compatible = "fixed-factor-clock";
-               clocks = <&parentclk>;
-               #clock-cells = <0>;
-               clock-div = <2>;
-               clock-mult = <1>;
-       };

diff --git a/Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml b/Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml
new file mode 100644 (file)
index 0000000..b567f80
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Binding for simple fixed factor rate clock sources
+
+maintainers:
+  - Michael Turquette <mturquette@baylibre.com>
+  - Stephen Boyd <sboyd@kernel.org>
+
+properties:
+  compatible:
+    enum:
+      - allwinner,sun4i-a10-pll3-2x-clk
+      - fixed-factor-clock
+
+  "#clock-cells":
+    const: 0
+
+  clocks:
+    maxItems: 1
+
+  clock-div:
+    description: Fixed divider
+    allOf:
+      - $ref: /schemas/types.yaml#/definitions/uint32
+      - minimum: 1
+
+  clock-mult:
+    description: Fixed multiplier
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+  clock-output-names:
+    maxItems: 1
+
+required:
+  - compatible
+  - clocks
+  - "#clock-cells"
+  - clock-div
+  - clock-mult
+
+additionalProperties: false
+
+examples:
+  - |
+    clock {
+      compatible = "fixed-factor-clock";
+      clocks = <&parentclk>;
+      #clock-cells = <0>;
+      clock-div = <2>;
+      clock-mult = <1>;
+    };
+...

diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
index 2895a5a..b09cb3d 100644 (file)
--- a/drivers/clk/mediatek/clk-mt2712.c
+++ b/drivers/clk/mediatek/clk-mt2712.c
@@ -223,6 +223,8 @@ static const struct mtk_fixed_factor top_divs[] = {
                4),
        FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1,
                3),
+       FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1,
+               3),
 };
 
 static const char * const axi_parents[] = {
@@ -594,7 +596,8 @@ static const char * const a1sys_hp_parents[] = {
        "apll1_ck",
        "apll1_d2",
        "apll1_d4",
-       "apll1_d8"
+       "apll1_d8",
+       "apll1_d3"
 };
 
 static const char * const a2sys_hp_parents[] = {
@@ -602,7 +605,8 @@ static const char * const a2sys_hp_parents[] = {
        "apll2_ck",
        "apll2_d2",
        "apll2_d4",
-       "apll2_d8"
+       "apll2_d8",
+       "apll2_d3"
 };
 
 static const char * const asm_l_parents[] = {

diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index 7ea2034..5ecf288 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -586,12 +586,12 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
        COMPOSITE(0, "dclk_lcdc0_src", mux_pll_src_cpll_gpll_p, 0,
                        RK2928_CLKSEL_CON(27), 0, 1, MFLAGS, 8, 8, DFLAGS,
                        RK2928_CLKGATE_CON(3), 1, GFLAGS),
-       MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, 0,
+       MUX(DCLK_LCDC0, "dclk_lcdc0", mux_rk3066_lcdc0_p, CLK_SET_RATE_PARENT,
                        RK2928_CLKSEL_CON(27), 4, 1, MFLAGS),
        COMPOSITE(0, "dclk_lcdc1_src", mux_pll_src_cpll_gpll_p, 0,
                        RK2928_CLKSEL_CON(28), 0, 1, MFLAGS, 8, 8, DFLAGS,
                        RK2928_CLKGATE_CON(3), 2, GFLAGS),
-       MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, 0,
+       MUX(DCLK_LCDC1, "dclk_lcdc1", mux_rk3066_lcdc1_p, CLK_SET_RATE_PARENT,
                        RK2928_CLKSEL_CON(28), 4, 1, MFLAGS),
 
        COMPOSITE_NOMUX(0, "cif1_pre", "cif_src", 0,

diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
index faa94ad..65ab5c2 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3328.c
+++ b/drivers/clk/rockchip/clk-rk3328.c
@@ -78,17 +78,17 @@ static struct rockchip_pll_rate_table rk3328_pll_rates[] = {
 
 static struct rockchip_pll_rate_table rk3328_pll_frac_rates[] = {
        /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
-       RK3036_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134217),
+       RK3036_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134218),
        /* vco = 1016064000 */
-       RK3036_PLL_RATE(983040000, 24, 983, 1, 1, 0, 671088),
+       RK3036_PLL_RATE(983040000, 24, 983, 1, 1, 0, 671089),
        /* vco = 983040000 */
-       RK3036_PLL_RATE(491520000, 24, 983, 2, 1, 0, 671088),
+       RK3036_PLL_RATE(491520000, 24, 983, 2, 1, 0, 671089),
        /* vco = 983040000 */
-       RK3036_PLL_RATE(61440000, 6, 215, 7, 2, 0, 671088),
+       RK3036_PLL_RATE(61440000, 6, 215, 7, 2, 0, 671089),
        /* vco = 860156000 */
-       RK3036_PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797894),
+       RK3036_PLL_RATE(56448000, 12, 451, 4, 4, 0, 9797895),
        /* vco = 903168000 */
-       RK3036_PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066329),
+       RK3036_PLL_RATE(40960000, 12, 409, 4, 5, 0, 10066330),
        /* vco = 819200000 */
        { /* sentinel */ },
 };

diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index c3f309d..9cfaca5 100644 (file)
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -26,7 +26,7 @@ struct samsung_clk_provider {
        void __iomem *reg_base;
        struct device *dev;
        spinlock_t lock;
-       /* clk_data must be the last entry due to variable lenght 'hws' array */
+       /* clk_data must be the last entry due to variable length 'hws' array */
        struct clk_hw_onecell_data clk_data;
 };
 

diff --git a/include/dt-bindings/clock/mt2712-clk.h b/include/dt-bindings/clock/mt2712-clk.h
index 7626583..c3b29df 100644 (file)
--- a/include/dt-bindings/clock/mt2712-clk.h
+++ b/include/dt-bindings/clock/mt2712-clk.h
@@ -228,7 +228,8 @@
 #define CLK_TOP_NFI2X_EN               189
 #define CLK_TOP_NFIECC_EN              190
 #define CLK_TOP_NFI1X_CK_EN            191
-#define CLK_TOP_NR_CLK                 192
+#define CLK_TOP_APLL2_D3               192
+#define CLK_TOP_NR_CLK                 193
 
 /* INFRACFG */