arm64: dts: r8a7795: Add cpuidle support for CA53 cores

Enables cpuidle (core shutdown) support for R-Car H3 CA53 cores.

Signed-off-by: Dien Pham <dien.pham.ry@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Link: https://lore.kernel.org/r/1547808474-19427-3-git-send-email-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index fb869cb..6675462 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -212,6 +212,7 @@
                        power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
                        next-level-cache = <&L2_CA53>;
                        enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_1>;
                        #cooling-cells = <2>;
                        dynamic-power-coefficient = <277>;
                        clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
@@ -226,6 +227,7 @@
                        power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
                        next-level-cache = <&L2_CA53>;
                        enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_1>;
                        clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
                        operating-points-v2 = <&cluster1_opp>;
                        capacity-dmips-mhz = <535>;
@@ -238,6 +240,7 @@
                        power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
                        next-level-cache = <&L2_CA53>;
                        enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_1>;
                        clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
                        operating-points-v2 = <&cluster1_opp>;
                        capacity-dmips-mhz = <535>;
@@ -250,6 +253,7 @@
                        power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
                        next-level-cache = <&L2_CA53>;
                        enable-method = "psci";
+                       cpu-idle-states = <&CPU_SLEEP_1>;
                        clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>;
                        operating-points-v2 = <&cluster1_opp>;
                        capacity-dmips-mhz = <535>;
@@ -280,6 +284,15 @@
                                exit-latency-us = <500>;
                                min-residency-us = <4000>;
                        };
+
+                       CPU_SLEEP_1: cpu-sleep-1 {
+                               compatible = "arm,idle-state";
+                               arm,psci-suspend-param = <0x0010000>;
+                               local-timer-stop;
+                               entry-latency-us = <700>;
+                               exit-latency-us = <700>;
+                               min-residency-us = <5000>;
+                       };
                };
        };