[X86] Avoid clobbering ESP/RSP in the epilogue.

Summary:
In r345197 ESP and RSP were added to GR32_TC/GR64_TC, allowing them to
be used for tail calls, but this also caused `findDeadCallerSavedReg` to
think they were acceptable targets for clobbering. Filter them out.

Fixes PR40289.

Patch by Geoffry Song!

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D56617

llvm-svn: 351146

diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp
index d722c75..984db12 100644 (file)
--- a/llvm/lib/Target/X86/X86FrameLowering.cpp
+++ b/llvm/lib/Target/X86/X86FrameLowering.cpp
@@ -185,7 +185,8 @@ static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
     }
 
     for (auto CS : AvailableRegs)
-      if (!Uses.count(CS) && CS != X86::RIP)
+      if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP &&
+          CS != X86::ESP)
         return CS;
   }
   }

diff --git a/llvm/test/CodeGen/X86/pr40289-64bit.ll b/llvm/test/CodeGen/X86/pr40289-64bit.ll
new file mode 100644 (file)
index 0000000..fd7e2d5
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr40289-64bit.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -mtriple=x86_64-pc-windows-msvc | FileCheck %s
+
+define cc 92 < 9 x i64 > @clobber() {
+  %1 = alloca i64
+  %2 = load volatile i64, i64* %1
+  ret < 9 x i64 > undef
+  ; CHECK-LABEL: clobber:
+  ; CHECK-NOT: popq %rsp
+  ; CHECK: addq $8, %rsp
+}

diff --git a/llvm/test/CodeGen/X86/pr40289.ll b/llvm/test/CodeGen/X86/pr40289.ll
new file mode 100644 (file)
index 0000000..abcb5fa
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr40289.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -mtriple=i686-pc-windows-msvc | FileCheck %s
+
+define < 3 x i32 > @clobber() {
+  %1 = alloca i32
+  %2 = load volatile i32, i32* %1
+  ret < 3 x i32 > undef
+  ; CHECK-LABEL: clobber:
+  ; CHECK-NOT: popl %esp
+  ; CHECK: addl $4, %esp
+}