drm/amdgpu: clean up memory/GDS/GWS/OA alignment code
authorMarek Olšák <marek.olsak@amd.com>
Tue, 22 Jan 2019 20:44:54 +0000 (15:44 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 1 Feb 2019 05:33:00 +0000 (00:33 -0500)
- move all adjustments into one place
- specify GDS/GWS/OA alignment in basic units of the heaps
- it looks like GDS alignment was 1 instead of 4

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

index f4f0021..d21dd2f 100644 (file)
@@ -54,10 +54,6 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
 
        memset(&bp, 0, sizeof(bp));
        *obj = NULL;
-       /* At least align on page size */
-       if (alignment < PAGE_SIZE) {
-               alignment = PAGE_SIZE;
-       }
 
        bp.size = size;
        bp.byte_align = alignment;
@@ -244,9 +240,6 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
                        return -EINVAL;
                }
                flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
-               /* GDS allocations must be DW aligned */
-               if (args->in.domains & AMDGPU_GEM_DOMAIN_GDS)
-                       size = ALIGN(size, 4);
        }
 
        if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
index 728e15e..fd9c4be 100644 (file)
@@ -426,12 +426,20 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
        size_t acc_size;
        int r;
 
-       page_align = roundup(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
-       if (bp->domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS |
-                         AMDGPU_GEM_DOMAIN_OA))
+       /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */
+       if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
+               /* GWS and OA don't need any alignment. */
+               page_align = bp->byte_align;
                size <<= PAGE_SHIFT;
-       else
+       } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) {
+               /* Both size and alignment must be a multiple of 4. */
+               page_align = ALIGN(bp->byte_align, 4);
+               size = ALIGN(size, 4) << PAGE_SHIFT;
+       } else {
+               /* Memory should be aligned at least to a page size. */
+               page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
                size = ALIGN(size, PAGE_SIZE);
+       }
 
        if (!amdgpu_bo_validate_size(adev, size, bp->domain))
                return -ENOMEM;
index b852abb..73e71e6 100644 (file)
@@ -1756,7 +1756,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
        }
 
        r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
-                                   PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
+                                   4, AMDGPU_GEM_DOMAIN_GDS,
                                    &adev->gds.gds_gfx_bo, NULL, NULL);
        if (r)
                return r;
@@ -1769,7 +1769,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
        }
 
        r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
-                                   PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
+                                   1, AMDGPU_GEM_DOMAIN_GWS,
                                    &adev->gds.gws_gfx_bo, NULL, NULL);
        if (r)
                return r;
@@ -1782,7 +1782,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
        }
 
        r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
-                                   PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
+                                   1, AMDGPU_GEM_DOMAIN_OA,
                                    &adev->gds.oa_gfx_bo, NULL, NULL);
        if (r)
                return r;