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drm: Fix ordering of bit fields in EDID structure leading huge vsync values.
author
Jesse Barnes
<jbarnes@virtuousgeek.org>
Mon, 23 Feb 2009 23:36:41 +0000
(15:36 -0800)
committer
Dave Airlie
<airlied@linux.ie>
Wed, 25 Feb 2009 04:11:00 +0000
(14:11 +1000)
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@linux.ie>
include/drm/drm_edid.h
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diff --git
a/include/drm/drm_edid.h
b/include/drm/drm_edid.h
index
c707c15
..
ff8d27a
100644
(file)
--- a/
include/drm/drm_edid.h
+++ b/
include/drm/drm_edid.h
@@
-58,10
+58,10
@@
struct detailed_pixel_timing {
u8 hsync_pulse_width_lo;
u8 vsync_pulse_width_lo:4;
u8 vsync_offset_lo:4;
- u8 hsync_pulse_width_hi:2;
- u8 hsync_offset_hi:2;
u8 vsync_pulse_width_hi:2;
u8 vsync_offset_hi:2;
+ u8 hsync_pulse_width_hi:2;
+ u8 hsync_offset_hi:2;
u8 width_mm_lo;
u8 height_mm_lo;
u8 height_mm_hi:4;