PCI: designware: Keep viewport fixed for IO transaction if num_viewport > 2

Most of the platforms have 3 or more viewports.  For such platforms, We do
not need to share viewports between IO and CFG.  Assign viewport 2 to IO
transactions in such cases.

Tested-by: Dong Bo <dongbo4@huawei.com>
Signed-off-by: Pratyush Anand <pratyush.anand@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>

diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index 6c5322c..1392c70 100644 (file)
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -17,6 +17,8 @@ Required properties:
 - num-lanes: number of lanes to use
 
 Optional properties:
+- num-viewport: number of view ports configured in hardware.  If a platform
+  does not specify it, the driver assumes 2.
 - num-lanes: number of lanes to use (this property should be specified unless
   the link is brought already up in BIOS)
 - reset-gpio: gpio pin number of power good signal
@@ -44,4 +46,5 @@ Example configuration:
                interrupts = <25>, <24>;
                #interrupt-cells = <1>;
                num-lanes = <1>;
+               num-viewport = <3>;
        };

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 085fde2..3846013 100644 (file)
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -61,6 +61,7 @@
 #define PCIE_ATU_VIEWPORT              0x900
 #define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
 #define PCIE_ATU_REGION_OUTBOUND       (0x0 << 31)
+#define PCIE_ATU_REGION_INDEX2         (0x2 << 0)
 #define PCIE_ATU_REGION_INDEX1         (0x1 << 0)
 #define PCIE_ATU_REGION_INDEX0         (0x0 << 0)
 #define PCIE_ATU_CR1                   0x904
@@ -616,6 +617,10 @@ int dw_pcie_host_init(struct pcie_port *pp)
        if (ret)
                pp->lanes = 0;
 
+       ret = of_property_read_u32(np, "num-viewport", &pp->num_viewport);
+       if (ret)
+               pp->num_viewport = 2;
+
        if (IS_ENABLED(CONFIG_PCI_MSI)) {
                if (!pp->ops->msi_host_init) {
                        pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
@@ -707,9 +712,10 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
                                  type, cpu_addr,
                                  busdev, cfg_size);
        ret = dw_pcie_cfg_read(va_cfg_base + where, size, val);
-       dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
-                                 PCIE_ATU_TYPE_IO, pp->io_base,
-                                 pp->io_bus_addr, pp->io_size);
+       if (pp->num_viewport <= 2)
+               dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+                                         PCIE_ATU_TYPE_IO, pp->io_base,
+                                         pp->io_bus_addr, pp->io_size);
 
        return ret;
 }
@@ -744,9 +750,10 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
                                  type, cpu_addr,
                                  busdev, cfg_size);
        ret = dw_pcie_cfg_write(va_cfg_base + where, size, val);
-       dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
-                                 PCIE_ATU_TYPE_IO, pp->io_base,
-                                 pp->io_bus_addr, pp->io_size);
+       if (pp->num_viewport <= 2)
+               dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
+                                         PCIE_ATU_TYPE_IO, pp->io_base,
+                                         pp->io_bus_addr, pp->io_size);
 
        return ret;
 }
@@ -882,10 +889,15 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
         * uses its own address translation component rather than ATU, so
         * we should not program the ATU here.
         */
-       if (!pp->ops->rd_other_conf)
+       if (!pp->ops->rd_other_conf) {
                dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1,
                                          PCIE_ATU_TYPE_MEM, pp->mem_base,
                                          pp->mem_bus_addr, pp->mem_size);
+               if (pp->num_viewport > 2)
+                       dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX2,
+                                                 PCIE_ATU_TYPE_IO, pp->io_base,
+                                                 pp->io_bus_addr, pp->io_size);
+       }
 
        dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
 

diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index e74cc4a..c8e5bc6 100644 (file)
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -44,6 +44,7 @@ struct pcie_port {
        struct resource         *busn;
        int                     irq;
        u32                     lanes;
+       u32                     num_viewport;
        struct pcie_host_ops    *ops;
        int                     msi_irq;
        struct irq_domain       *irq_domain;