gpio: aspeed: Fix incorrect offset of read back register.

The offset of the current read back register is the value of the gpio pin,
not the value written for the gpio output.
This patch fix it to avoid the other gpio output value controlled by the
same register being set incorrectly.

Fixes: 7ad889b0f37a ("gpio: Add Aspeed GPIO driver")
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>

diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c
index a8a2afc..2c5415c 100644 (file)
--- a/drivers/gpio/gpio-aspeed.c
+++ b/drivers/gpio/gpio-aspeed.c
@@ -211,7 +211,7 @@ static int aspeed_gpio_direction_output(struct udevice *dev, unsigned int offset
        struct aspeed_gpio_priv *priv = dev_get_priv(dev);
        const struct aspeed_gpio_bank *bank = to_bank(offset);
        u32 dir = readl(bank_reg(priv, bank, reg_dir));
-       u32 output = readl(bank_reg(priv, bank, reg_val));
+       u32 output = readl(bank_reg(priv, bank, reg_rdata));
 
        dir |= GPIO_BIT(offset);
        writel(dir, bank_reg(priv, bank, reg_dir));
@@ -239,7 +239,7 @@ aspeed_gpio_set_value(struct udevice *dev, unsigned int offset, int value)
 {
        struct aspeed_gpio_priv *priv = dev_get_priv(dev);
        const struct aspeed_gpio_bank *bank = to_bank(offset);
-       u32 data = readl(bank_reg(priv, bank, reg_val));
+       u32 data = readl(bank_reg(priv, bank, reg_rdata));
 
        if (value)
                data |= GPIO_BIT(offset);