[AArch64][SVE] Enable DiagnosticPredicates for SVE LD1 instructions.

This patch extends the PredicateMethod of AsmOperands used in SVE's
LD1 instructions with a DiagnosticPredicate. This makes them 'context
sensitive' to the operand that has been parsed and tells the user to
use the right register (with expected shift/extend), rather than telling
the immediate is out of range when it actually parsed a register.

Patch [2/2] in a series to improve assembler diagnostics for SVE:
-  Patch [1/2]: https://reviews.llvm.org/D45879
-  Patch [2/2]: https://reviews.llvm.org/D45880

Reviewers: olista01, stoklund, craig.topper, mcrosier, rengolin, echristo, fhahn, SjoerdMeijer, evandro, javed.absar

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D45880

llvm-svn: 330934

diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 6af1207..2f042cd 100644 (file)
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -506,19 +506,24 @@ public:
 
   template <int Width> bool isSImm() const { return isSImmScaled<Width, 1>(); }
 
-  template <int Bits, int Scale> bool isSImmScaled() const {
+  template <int Bits, int Scale>
+  DiagnosticPredicate isSImmScaled() const {
     if (!isImm())
-      return false;
+      return DiagnosticPredicateTy::NoMatch;
+
     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
     if (!MCE)
-      return false;
+      return DiagnosticPredicateTy::NoMatch;
 
     int64_t Shift = Bits - 1;
     int64_t MinVal = (int64_t(1) << Shift) * -Scale;
     int64_t MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
 
     int64_t Val = MCE->getValue();
-    return Val >= MinVal && Val <= MaxVal && (Val % Scale) == 0;
+    if (Val >= MinVal && Val <= MaxVal && (Val % Scale) == 0)
+      return DiagnosticPredicateTy::Match;
+
+    return DiagnosticPredicateTy::NearMatch;
   }
 
   bool isSVEPattern() const {
@@ -859,10 +864,16 @@ public:
 
   template <int ElementWidth, unsigned Class,
             AArch64_AM::ShiftExtendType ShiftExtendTy, int ShiftWidth>
-  bool isSVEVectorRegWithShiftExtend() const {
-    return Kind == k_Register && isSVEVectorRegOfWidth<ElementWidth, Class>() &&
-           ShiftExtendTy == getShiftExtendType() &&
-           getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
+  DiagnosticPredicate isSVEVectorRegWithShiftExtend() const {
+    if (Kind != k_Register || Reg.Kind != RegKind::SVEDataVector)
+      return DiagnosticPredicateTy::NoMatch;
+
+    if (isSVEVectorRegOfWidth<ElementWidth, Class>() &&
+        ShiftExtendTy == getShiftExtendType() &&
+        getShiftExtendAmount() == Log2_32(ShiftWidth / 8))
+      return DiagnosticPredicateTy::Match;
+
+    return DiagnosticPredicateTy::NearMatch;
   }
 
   bool isGPR32as64() const {
@@ -899,12 +910,14 @@ public:
   }
 
   template <unsigned RegClassID, int ExtWidth>
-  bool isGPR64WithShiftExtend() const {
-    if (!isGPR64<RegClassID>())
-      return false;
-
-    return getShiftExtendType() == AArch64_AM::LSL &&
-           getShiftExtendAmount() == Log2_32(ExtWidth / 8);
+  DiagnosticPredicate isGPR64WithShiftExtend() const {
+    if (Kind != k_Register || Reg.Kind != RegKind::Scalar)
+      return DiagnosticPredicateTy::NoMatch;
+
+    if (isGPR64<RegClassID>() && getShiftExtendType() == AArch64_AM::LSL &&
+        getShiftExtendAmount() == Log2_32(ExtWidth / 8))
+      return DiagnosticPredicateTy::Match;
+    return DiagnosticPredicateTy::NearMatch;
   }
 
   /// Is this a vector list with the type implicit (presumably attached to the

diff --git a/llvm/test/MC/AArch64/SVE/ld1b-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1b-diagnostics.s
index b812c5a..a1b4e0f 100644 (file)
--- a/llvm/test/MC/AArch64/SVE/ld1b-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ld1b-diagnostics.s
@@ -91,22 +91,22 @@ ld1b { v0.2d }, p0/z, [x1, #1, MUL VL]
 // Invalid scalar + scalar addressing modes
 
 ld1b z0.b, p0/z, [x0, xzr]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
 // CHECK-NEXT: ld1b z0.b, p0/z, [x0, xzr]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1b z0.b, p0/z, [x0, x0, lsl #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
 // CHECK-NEXT: ld1b z0.b, p0/z, [x0, x0, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1b z0.b, p0/z, [x0, w0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
 // CHECK-NEXT: ld1b z0.b, p0/z, [x0, w0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1b z0.b, p0/z, [x0, w0, uxtw]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
 // CHECK-NEXT: ld1b z0.b, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -115,41 +115,41 @@ ld1b z0.b, p0/z, [x0, w0, uxtw]
 // Invalid scalar + vector addressing modes
 
 ld1b z0.d, p0/z, [x0, z0.b]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.b]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1b z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1b z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1b z0.s, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1b z0.s, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1b z0.s, p0/z, [x0, z0.s, uxtw #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1b z0.s, p0/z, [x0, z0.s, uxtw #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1b z0.s, p0/z, [x0, z0.s, lsl #0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1b z0.s, p0/z, [x0, z0.s, lsl #0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1b z0.d, p0/z, [x0, z0.d, lsl #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.d, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1b z0.d, p0/z, [x0, z0.d, sxtw #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.d, sxtw #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/llvm/test/MC/AArch64/SVE/ld1d-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1d-diagnostics.s
index 02f9986..9be7180 100644 (file)
--- a/llvm/test/MC/AArch64/SVE/ld1d-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ld1d-diagnostics.s
@@ -46,27 +46,27 @@ ld1d { v0.2d }, p0/z, [x1, #1, MUL VL]
 // Invalid scalar + scalar addressing modes
 
 ld1d z0.d, p0/z, [x0, x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1d z0.d, p0/z, [x0, xzr]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, xzr]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1d z0.d, p0/z, [x0, x0, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, x0, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1d z0.d, p0/z, [x0, w0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, w0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1d z0.d, p0/z, [x0, w0, uxtw]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3'
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -75,17 +75,17 @@ ld1d z0.d, p0/z, [x0, w0, uxtw]
 // Invalid scalar + vector addressing modes
 
 ld1d z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1d z0.d, p0/z, [x0, z0.d, uxtw #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.d, uxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1d z0.d, p0/z, [x0, z0.d, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.d, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

diff --git a/llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s
index 3bbb8f9..a9d8992 100644 (file)
--- a/llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s
@@ -76,27 +76,27 @@ ld1h { v0.2d }, p0/z, [x1, #1, MUL VL]
 // Invalid scalar + scalar addressing modes
 
 ld1h z0.h, p0/z, [x0, x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
 // CHECK-NEXT: ld1h z0.h, p0/z, [x0, x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h z0.h, p0/z, [x0, xzr]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
 // CHECK-NEXT: ld1h z0.h, p0/z, [x0, xzr]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h z0.h, p0/z, [x0, x0, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
 // CHECK-NEXT: ld1h z0.h, p0/z, [x0, x0, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h z0.h, p0/z, [x0, w0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
 // CHECK-NEXT: ld1h z0.h, p0/z, [x0, w0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h z0.h, p0/z, [x0, w0, uxtw]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
 // CHECK-NEXT: ld1h z0.h, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -105,36 +105,36 @@ ld1h z0.h, p0/z, [x0, w0, uxtw]
 // Invalid scalar + vector addressing modes
 
 ld1h z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h z0.s, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1h z0.s, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h z0.s, p0/z, [x0, z0.s, uxtw #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1h z0.s, p0/z, [x0, z0.s, uxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h z0.s, p0/z, [x0, z0.s, lsl #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1h z0.s, p0/z, [x0, z0.s, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h z0.d, p0/z, [x0, z0.d, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.d, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h z0.d, p0/z, [x0, z0.d, sxtw #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.d, sxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/llvm/test/MC/AArch64/SVE/ld1sb-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1sb-diagnostics.s
index 130e571..3431099 100644 (file)
--- a/llvm/test/MC/AArch64/SVE/ld1sb-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ld1sb-diagnostics.s
@@ -90,22 +90,22 @@ ld1sb { v0.2d }, p0/z, [x1, #1, MUL VL]
 // Invalid scalar + scalar addressing modes
 
 ld1sb z0.h, p0/z, [x0, xzr]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
 // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, xzr]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sb z0.h, p0/z, [x0, x0, lsl #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
 // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, x0, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sb z0.h, p0/z, [x0, w0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
 // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, w0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sb z0.h, p0/z, [x0, w0, uxtw]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift
 // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -113,41 +113,41 @@ ld1sb z0.h, p0/z, [x0, w0, uxtw]
 // Invalid scalar + vector addressing modes
 
 ld1sb z0.d, p0/z, [x0, z0.b]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.b]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sb z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sb z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sb z0.s, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sb z0.s, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sb z0.s, p0/z, [x0, z0.s, uxtw #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sb z0.s, p0/z, [x0, z0.s, uxtw #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sb z0.s, p0/z, [x0, z0.s, lsl #0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sb z0.s, p0/z, [x0, z0.s, lsl #0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sb z0.d, p0/z, [x0, z0.d, lsl #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.d, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sb z0.d, p0/z, [x0, z0.d, sxtw #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.d, sxtw #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s
index 6ecc83d..bbaf666 100644 (file)
--- a/llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s
@@ -75,27 +75,27 @@ ld1sh { v0.2d }, p0/z, [x1, #1, MUL VL]
 // Invalid scalar + scalar addressing modes
 
 ld1sh z0.s, p0/z, [x0, x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
 // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z0.s, p0/z, [x0, xzr]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
 // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, xzr]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z0.s, p0/z, [x0, x0, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
 // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, x0, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z0.s, p0/z, [x0, w0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
 // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, w0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z0.s, p0/z, [x0, w0, uxtw]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
 // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -104,36 +104,36 @@ ld1sh z0.s, p0/z, [x0, w0, uxtw]
 // Invalid scalar + vector addressing modes
 
 ld1sh z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z0.s, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z0.s, p0/z, [x0, z0.s, uxtw #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, z0.s, uxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z0.s, p0/z, [x0, z0.s, lsl #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, z0.s, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z0.d, p0/z, [x0, z0.d, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.d, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sh z0.d, p0/z, [x0, z0.d, sxtw #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.d, sxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/llvm/test/MC/AArch64/SVE/ld1sw-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1sw-diagnostics.s
index 3017ff6..0363e0b 100644 (file)
--- a/llvm/test/MC/AArch64/SVE/ld1sw-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ld1sw-diagnostics.s
@@ -60,27 +60,27 @@ ld1sw { v0.2d }, p0/z, [x1, #1, MUL VL]
 // Invalid scalar + scalar addressing modes
 
 ld1sw z0.d, p0/z, [x0, x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, xzr]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, xzr]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, x0, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, x0, lsl #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, w0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, w0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, w0, uxtw]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -89,27 +89,27 @@ ld1sw z0.d, p0/z, [x0, w0, uxtw]
 // Invalid scalar + vector addressing modes
 
 ld1sw z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, z0.d, uxtw #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, uxtw #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, z0.d, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, lsl #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -119,11 +119,11 @@ ld1sw z0.d, p0/z, [x0, z0.d, lsl]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, z0.d, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, lsl #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1sw z0.d, p0/z, [x0, z0.d, sxtw #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, sxtw #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/llvm/test/MC/AArch64/SVE/ld1w-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1w-diagnostics.s
index e9fb052..86e12f5 100644 (file)
--- a/llvm/test/MC/AArch64/SVE/ld1w-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ld1w-diagnostics.s
@@ -61,27 +61,27 @@ ld1w { v0.2d }, p0/z, [x1, #1, MUL VL]
 // Invalid scalar + scalar addressing modes
 
 ld1w z0.s, p0/z, [x0, x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w z0.s, p0/z, [x0, xzr]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, xzr]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w z0.s, p0/z, [x0, x0, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, x0, lsl #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w z0.s, p0/z, [x0, w0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, w0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w z0.s, p0/z, [x0, w0, uxtw]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2'
 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
@@ -90,36 +90,36 @@ ld1w z0.s, p0/z, [x0, w0, uxtw]
 // Invalid scalar + vector addressing modes
 
 ld1w z0.d, p0/z, [x0, z0.h]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.h]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w z0.d, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w z0.s, p0/z, [x0, z0.s]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, z0.s]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w z0.s, p0/z, [x0, z0.s, uxtw #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, z0.s, uxtw #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w z0.s, p0/z, [x0, z0.s, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
 // CHECK-NEXT: ld1w z0.s, p0/z, [x0, z0.s, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w z0.d, p0/z, [x0, z0.d, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.d, lsl #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w z0.d, p0/z, [x0, z0.d, sxtw #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.d, sxtw #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

diff --git a/llvm/test/MC/AArch64/SVE/ldff1d-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1d-diagnostics.s
index 534a670..60ab31f 100644 (file)
--- a/llvm/test/MC/AArch64/SVE/ldff1d-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1d-diagnostics.s
@@ -30,22 +30,22 @@ ldff1d z4.d, p8/z, [x0]
 // Invalid scalar + scalar addressing modes
 
 ldff1d z0.d, p0/z, [x0, sp]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, sp]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1d z0.d, p0/z, [x0, x0, lsl #1]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, x0, lsl #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1d z0.d, p0/z, [x0, w0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, w0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1d z0.d, p0/z, [x0, w0, uxtw]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3'
 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

diff --git a/llvm/test/MC/AArch64/SVE/ldff1sh-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1sh-diagnostics.s
index a652df5..aa05677 100644 (file)
--- a/llvm/test/MC/AArch64/SVE/ldff1sh-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1sh-diagnostics.s
@@ -25,22 +25,22 @@ ldff1sh z4.d, p8/z, [x0]
 // Invalid scalar + scalar addressing modes
 
 ldff1sh z0.s, p0/z, [x0, sp]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
 // CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, sp]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sh z0.s, p0/z, [x0, x0, lsl #2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
 // CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, x0, lsl #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sh z0.s, p0/z, [x0, w0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
 // CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, w0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sh z0.s, p0/z, [x0, w0, uxtw]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1'
 // CHECK-NEXT: ldff1sh z0.s, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

diff --git a/llvm/test/MC/AArch64/SVE/ldff1sw-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1sw-diagnostics.s
index bb7f771..765b3ee 100644 (file)
--- a/llvm/test/MC/AArch64/SVE/ldff1sw-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1sw-diagnostics.s
@@ -20,22 +20,22 @@ ldff1sw z4.d, p8/z, [x0]
 // Invalid scalar + scalar addressing modes
 
 ldff1sw z0.d, p0/z, [x0, sp]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
 // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, sp]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sw z0.d, p0/z, [x0, x0, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
 // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, x0, lsl #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sw z0.d, p0/z, [x0, w0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
 // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, w0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1sw z0.d, p0/z, [x0, w0, uxtw]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
 // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

diff --git a/llvm/test/MC/AArch64/SVE/ldff1w-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1w-diagnostics.s
index 1e1582c..cdf12e6 100644 (file)
--- a/llvm/test/MC/AArch64/SVE/ldff1w-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1w-diagnostics.s
@@ -30,22 +30,22 @@ ldff1w z4.d, p8/z, [x0]
 // Invalid scalar + scalar addressing modes
 
 ldff1w z0.s, p0/z, [x0, sp]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
 // CHECK-NEXT: ldff1w z0.s, p0/z, [x0, sp]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1w z0.s, p0/z, [x0, x0, lsl #3]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
 // CHECK-NEXT: ldff1w z0.s, p0/z, [x0, x0, lsl #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1w z0.s, p0/z, [x0, w0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
 // CHECK-NEXT: ldff1w z0.s, p0/z, [x0, w0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldff1w z0.s, p0/z, [x0, w0, uxtw]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2'
 // CHECK-NEXT: ldff1w z0.s, p0/z, [x0, w0, uxtw]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: