amdgpu/pm: Replace smu11 usage of sprintf with sysfs_emit

 modification of smu11 files
  arcturus_ppt.c
  sienna_cichlid_ppt.c
  vangogh_ppt.c

=== Test ===
AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | awk '{print $9}'`
HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}
LOGFILE=pp_printf.test.log

lspci -nn | grep "VGA\|Display"  > $LOGFILE
FILES="pp_dpm_sclk
pp_power_profile_mode "

for f in $FILES
do
  echo === $f === >> $LOGFILE
  cat $HWMON_DIR/device/$f >> $LOGFILE
done
cat $LOGFILE

Signed-off-by: Darren Powell <darren.powell@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 6ec8492..8ab5878 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -756,7 +756,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
        uint32_t gen_speed, lane_width;
 
        if (amdgpu_ras_intr_triggered())
-               return snprintf(buf, PAGE_SIZE, "unavailable\n");
+               return sysfs_emit(buf, "unavailable\n");
 
        dpm_context = smu_dpm->dpm_context;
 
@@ -780,7 +780,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
                 * And it's safe to assume that is always the current clock.
                 */
                for (i = 0; i < clocks.num_levels; i++)
-                       size += sprintf(buf + size, "%d: %uMhz %s\n", i,
+                       size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
                                        clocks.data[i].clocks_in_khz / 1000,
                                        (clocks.num_levels == 1) ? "*" :
                                        (arcturus_freqs_in_same_level(
@@ -803,7 +803,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
                }
 
                for (i = 0; i < clocks.num_levels; i++)
-                       size += sprintf(buf + size, "%d: %uMhz %s\n",
+                       size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
                                i, clocks.data[i].clocks_in_khz / 1000,
                                (clocks.num_levels == 1) ? "*" :
                                (arcturus_freqs_in_same_level(
@@ -826,7 +826,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
                }
 
                for (i = 0; i < clocks.num_levels; i++)
-                       size += sprintf(buf + size, "%d: %uMhz %s\n",
+                       size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
                                i, clocks.data[i].clocks_in_khz / 1000,
                                (clocks.num_levels == 1) ? "*" :
                                (arcturus_freqs_in_same_level(
@@ -849,7 +849,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
                }
 
                for (i = 0; i < single_dpm_table->count; i++)
-                       size += sprintf(buf + size, "%d: %uMhz %s\n",
+                       size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
                                i, single_dpm_table->dpm_levels[i].value,
                                (clocks.num_levels == 1) ? "*" :
                                (arcturus_freqs_in_same_level(
@@ -872,7 +872,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
                }
 
                for (i = 0; i < single_dpm_table->count; i++)
-                       size += sprintf(buf + size, "%d: %uMhz %s\n",
+                       size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
                                i, single_dpm_table->dpm_levels[i].value,
                                (clocks.num_levels == 1) ? "*" :
                                (arcturus_freqs_in_same_level(
@@ -895,7 +895,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
                }
 
                for (i = 0; i < single_dpm_table->count; i++)
-                       size += sprintf(buf + size, "%d: %uMhz %s\n",
+                       size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
                                i, single_dpm_table->dpm_levels[i].value,
                                (clocks.num_levels == 1) ? "*" :
                                (arcturus_freqs_in_same_level(
@@ -906,7 +906,7 @@ static int arcturus_print_clk_levels(struct smu_context *smu,
        case SMU_PCIE:
                gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
                lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
-               size += sprintf(buf + size, "0: %s %s %dMhz *\n",
+               size += sysfs_emit_at(buf, size, "0: %s %s %dMhz *\n",
                                (gen_speed == 0) ? "2.5GT/s," :
                                (gen_speed == 1) ? "5.0GT/s," :
                                (gen_speed == 2) ? "8.0GT/s," :
@@ -1272,11 +1272,11 @@ static int arcturus_get_power_profile_mode(struct smu_context *smu,
                return result;
 
        if (smu_version >= 0x360d00)
-               size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
+               size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
                        title[0], title[1], title[2], title[3], title[4], title[5],
                        title[6], title[7], title[8], title[9], title[10]);
        else
-               size += sprintf(buf + size, "%16s\n",
+               size += sysfs_emit_at(buf, size, "%16s\n",
                        title[0]);
 
        for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
@@ -1302,11 +1302,11 @@ static int arcturus_get_power_profile_mode(struct smu_context *smu,
                        }
                }
 
-               size += sprintf(buf + size, "%2d %14s%s\n",
+               size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
                        i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
 
                if (smu_version >= 0x360d00) {
-                       size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
+                       size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
                                " ",
                                0,
                                "GFXCLK",
@@ -1320,7 +1320,7 @@ static int arcturus_get_power_profile_mode(struct smu_context *smu,
                                activity_monitor.Gfx_PD_Data_error_coeff,
                                activity_monitor.Gfx_PD_Data_error_rate_coeff);
 
-                       size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
+                       size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
                                " ",
                                1,
                                "UCLK",

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 261ef8c..561f6bc 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1088,7 +1088,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
                                if (ret)
                                        goto print_clk_out;
 
-                               size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
+                               size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
                                                cur_value == value ? "*" : "");
                        }
                } else {
@@ -1110,7 +1110,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
                        }
 
                        for (i = 0; i < count; i++) {
-                               size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
+                               size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
                                                cur_value  == freq_values[i] ? "*" : "");
                        }
 
@@ -1121,7 +1121,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
                lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
                GET_PPTABLE_MEMBER(LclkFreq, &table_member);
                for (i = 0; i < NUM_LINK_LEVELS; i++)
-                       size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
+                       size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
                                        (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
                                        (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
                                        (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
@@ -1144,8 +1144,8 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
                if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
                        break;
 
-               size += sprintf(buf + size, "OD_SCLK:\n");
-               size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
+               size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
+               size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
                break;
 
        case SMU_OD_MCLK:
@@ -1155,8 +1155,8 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
                if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
                        break;
 
-               size += sprintf(buf + size, "OD_MCLK:\n");
-               size += sprintf(buf + size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
+               size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
+               size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
                break;
 
        case SMU_OD_VDDGFX_OFFSET:
@@ -1172,22 +1172,22 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
                     (smu_version < 0x003a2900))
                        break;
 
-               size += sprintf(buf + size, "OD_VDDGFX_OFFSET:\n");
-               size += sprintf(buf + size, "%dmV\n", od_table->VddGfxOffset);
+               size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
+               size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset);
                break;
 
        case SMU_OD_RANGE:
                if (!smu->od_enabled || !od_table || !od_settings)
                        break;
 
-               size = sprintf(buf, "%s:\n", "OD_RANGE");
+               size = sysfs_emit(buf, "%s:\n", "OD_RANGE");
 
                if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
                        sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
                                                            &min_value, NULL);
                        sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
                                                            NULL, &max_value);
-                       size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
+                       size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
                                        min_value, max_value);
                }
 
@@ -1196,7 +1196,7 @@ static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
                                                            &min_value, NULL);
                        sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
                                                            NULL, &max_value);
-                       size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
+                       size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
                                        min_value, max_value);
                }
                break;
@@ -1419,7 +1419,7 @@ static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *
        if (!buf)
                return -EINVAL;
 
-       size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
+       size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
                        title[0], title[1], title[2], title[3], title[4], title[5],
                        title[6], title[7], title[8], title[9], title[10]);
 
@@ -1439,10 +1439,10 @@ static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *
                        return result;
                }
 
-               size += sprintf(buf + size, "%2d %14s%s:\n",
+               size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
                        i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
 
-               size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
+               size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
                        " ",
                        0,
                        "GFXCLK",
@@ -1456,7 +1456,7 @@ static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *
                        activity_monitor->Gfx_PD_Data_error_coeff,
                        activity_monitor->Gfx_PD_Data_error_rate_coeff);
 
-               size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
+               size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
                        " ",
                        1,
                        "SOCCLK",
@@ -1470,7 +1470,7 @@ static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *
                        activity_monitor->Fclk_PD_Data_error_coeff,
                        activity_monitor->Fclk_PD_Data_error_rate_coeff);
 
-               size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
+               size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
                        " ",
                        2,
                        "MEMLK",

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index bcaaa08..6eb50b0 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -592,28 +592,28 @@ static int vangogh_print_legacy_clk_levels(struct smu_context *smu,
        switch (clk_type) {
        case SMU_OD_SCLK:
                if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
-                       size = sprintf(buf, "%s:\n", "OD_SCLK");
-                       size += sprintf(buf + size, "0: %10uMhz\n",
+                       size = sysfs_emit(buf, "%s:\n", "OD_SCLK");
+                       size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
                        (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
-                       size += sprintf(buf + size, "1: %10uMhz\n",
+                       size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
                        (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
                }
                break;
        case SMU_OD_CCLK:
                if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
-                       size = sprintf(buf, "CCLK_RANGE in Core%d:\n",  smu->cpu_core_id_select);
-                       size += sprintf(buf + size, "0: %10uMhz\n",
+                       size = sysfs_emit(buf, "CCLK_RANGE in Core%d:\n",  smu->cpu_core_id_select);
+                       size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
                        (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
-                       size += sprintf(buf + size, "1: %10uMhz\n",
+                       size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
                        (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
                }
                break;
        case SMU_OD_RANGE:
                if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
-                       size = sprintf(buf, "%s:\n", "OD_RANGE");
-                       size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
+                       size = sysfs_emit(buf, "%s:\n", "OD_RANGE");
+                       size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
                                smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
-                       size += sprintf(buf + size, "CCLK: %7uMhz %10uMhz\n",
+                       size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
                                smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
                }
                break;
@@ -656,14 +656,14 @@ static int vangogh_print_legacy_clk_levels(struct smu_context *smu,
                                return ret;
                        if (!value)
                                continue;
-                       size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
+                       size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
                                        cur_value == value ? "*" : "");
                        if (cur_value == value)
                                cur_value_match_level = true;
                }
 
                if (!cur_value_match_level)
-                       size += sprintf(buf + size, "   %uMhz *\n", cur_value);
+                       size += sysfs_emit_at(buf, size, "   %uMhz *\n", cur_value);
                break;
        default:
                break;
@@ -691,28 +691,28 @@ static int vangogh_print_clk_levels(struct smu_context *smu,
        switch (clk_type) {
        case SMU_OD_SCLK:
                if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
-                       size = sprintf(buf, "%s:\n", "OD_SCLK");
-                       size += sprintf(buf + size, "0: %10uMhz\n",
+                       size = sysfs_emit(buf, "%s:\n", "OD_SCLK");
+                       size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
                        (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
-                       size += sprintf(buf + size, "1: %10uMhz\n",
+                       size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
                        (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
                }
                break;
        case SMU_OD_CCLK:
                if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
-                       size = sprintf(buf, "CCLK_RANGE in Core%d:\n",  smu->cpu_core_id_select);
-                       size += sprintf(buf + size, "0: %10uMhz\n",
+                       size = sysfs_emit(buf, "CCLK_RANGE in Core%d:\n",  smu->cpu_core_id_select);
+                       size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
                        (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
-                       size += sprintf(buf + size, "1: %10uMhz\n",
+                       size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
                        (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
                }
                break;
        case SMU_OD_RANGE:
                if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
-                       size = sprintf(buf, "%s:\n", "OD_RANGE");
-                       size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
+                       size = sysfs_emit(buf, "%s:\n", "OD_RANGE");
+                       size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
                                smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
-                       size += sprintf(buf + size, "CCLK: %7uMhz %10uMhz\n",
+                       size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
                                smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
                }
                break;
@@ -755,14 +755,14 @@ static int vangogh_print_clk_levels(struct smu_context *smu,
                                return ret;
                        if (!value)
                                continue;
-                       size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
+                       size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
                                        cur_value == value ? "*" : "");
                        if (cur_value == value)
                                cur_value_match_level = true;
                }
 
                if (!cur_value_match_level)
-                       size += sprintf(buf + size, "   %uMhz *\n", cur_value);
+                       size += sysfs_emit_at(buf, size, "   %uMhz *\n", cur_value);
                break;
        default:
                break;
@@ -1035,7 +1035,7 @@ static int vangogh_get_power_profile_mode(struct smu_context *smu,
                if (workload_type < 0)
                        continue;
 
-               size += sprintf(buf + size, "%2d %14s%s\n",
+               size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
                        i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
        }