return false;
}
+/* Check if INSN is a BTI J insn. */
+static bool
+aarch64_bti_j_insn_p (rtx_insn *insn)
+{
+ if (!insn || !INSN_P (insn))
+ return false;
+
+ rtx pat = PATTERN (insn);
+ return GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_BTI_J;
+}
+
/* Insert the BTI instruction. */
/* This is implemented as a late RTL pass that runs before branch
shortening and does the following. */
for (j = GET_NUM_ELEM (vec) - 1; j >= 0; --j)
{
label = as_a <rtx_insn *> (XEXP (RTVEC_ELT (vec, j), 0));
+ rtx_insn *next = next_nonnote_nondebug_insn (label);
+ if (aarch64_bti_j_insn_p (next))
+ continue;
+
bti_insn = gen_bti_j ();
emit_insn_after (bti_insn, label);
}