Reuses the pass that was implemented for ANV.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8751>
Rapid packed math (16bit-vectorization) on RADV
VK_KHR_workgroup_memory_explicit_layout on Intel, RADV
DRM format modifiers for AMD.
-VK_KHR_zero_initialize_workgroup_memory on Intel
+VK_KHR_zero_initialize_workgroup_memory on Intel, RADV
features->workgroupMemoryExplicitLayout16BitAccess = true;
break;
}
+ case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ZERO_INITIALIZE_WORKGROUP_MEMORY_FEATURES_KHR: {
+ VkPhysicalDeviceZeroInitializeWorkgroupMemoryFeaturesKHR *features =
+ (VkPhysicalDeviceZeroInitializeWorkgroupMemoryFeaturesKHR*)ext;
+ features->shaderZeroInitializeWorkgroupMemory = true;
+ break;
+ }
default:
break;
}
Extension('VK_KHR_workgroup_memory_explicit_layout', 1, True),
Extension('VK_KHR_xcb_surface', 6, 'VK_USE_PLATFORM_XCB_KHR'),
Extension('VK_KHR_xlib_surface', 6, 'VK_USE_PLATFORM_XLIB_KHR'),
+ Extension('VK_KHR_zero_initialize_workgroup_memory', 1, True),
Extension('VK_EXT_4444_formats', 1, True),
Extension('VK_EXT_acquire_xlib_display', 1, 'VK_USE_PLATFORM_XLIB_XRANDR_EXT'),
Extension('VK_EXT_buffer_device_address', 2, True),
}
NIR_PASS_V(nir, nir_lower_explicit_io,
nir_var_mem_shared, nir_address_format_32bit_offset);
+
+ if (nir->info.cs.zero_initialize_shared_memory &&
+ nir->info.cs.shared_size > 0) {
+ const unsigned chunk_size = 16; /* max single store size */
+ const unsigned shared_size = ALIGN(nir->info.cs.shared_size, chunk_size);
+ NIR_PASS_V(nir, nir_zero_initialize_shared_memory,
+ shared_size, chunk_size);
+ }
}
nir_lower_explicit_io(nir, nir_var_mem_global,