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ARM: configs: qcom_defconfig: Enable SDX55 A7 PLL and APCS clock driver
authorManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thu, 8 Apr 2021 17:09:25 +0000 (22:39 +0530)
committerBjorn Andersson <bjorn.andersson@linaro.org>
Wed, 14 Apr 2021 02:21:14 +0000 (21:21 -0500)
Enable A7 PLL driver and APCS clock driver on SDX55 platform.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20210408170930.91834-3-manivannan.sadhasivam@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
arch/arm/configs/qcom_defconfig patch | blob | history

diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index 0b9da27..02f6185 100644 (file)
--- a/arch/arm/configs/qcom_defconfig
+++ b/arch/arm/configs/qcom_defconfig
@@ -215,6 +215,8 @@ CONFIG_DMADEVICES=y
 CONFIG_QCOM_BAM_DMA=y
 CONFIG_STAGING=y
 CONFIG_COMMON_CLK_QCOM=y
+CONFIG_QCOM_A7PLL=y
+CONFIG_QCOM_CLK_APCS_SDX55=y
 CONFIG_QCOM_CLK_RPM=y
 CONFIG_QCOM_CLK_RPMH=y
 CONFIG_QCOM_CLK_SMD_RPM=y
Domain: System / Kernel;