Add missing barrier to HOST in memory_barrier test

The test was lacking a barrier between device write access and
validation of the data on host.

Components: Vulkan

VK-GL-CTS Issue: 2359

Affects: dEQP-VK.memory_model.message_passing.*

Change-Id: Ia75277aaa2c7e25bff807cd3c6ebe14513403bfc

diff --git a/external/vulkancts/modules/vulkan/memory_model/vktMemoryModelMessagePassing.cpp b/external/vulkancts/modules/vulkan/memory_model/vktMemoryModelMessagePassing.cpp
index f101267..02b4ad2 100644 (file)
--- a/external/vulkancts/modules/vulkan/memory_model/vktMemoryModelMessagePassing.cpp
+++ b/external/vulkancts/modules/vulkan/memory_model/vktMemoryModelMessagePassing.cpp
@@ -1589,7 +1589,13 @@ tcu::TestStatus MemoryModelTestInstance::iterate (void)
                }
 
                if (x == NUM_SUBMITS - 1)
+               {
                        vk.cmdCopyBuffer(*cmdBuffer, **buffers[2], **copyBuffer, 1, &copyParams);
+                       memBarrier.srcAccessMask = VK_ACCESS_TRANSFER_WRITE_BIT;
+                       memBarrier.dstAccessMask = VK_ACCESS_HOST_READ_BIT;
+                       vk.cmdPipelineBarrier(*cmdBuffer, VK_PIPELINE_STAGE_TRANSFER_BIT, VK_PIPELINE_STAGE_HOST_BIT,
+                               0, 1, &memBarrier, 0, DE_NULL, 0, DE_NULL);
+               }
 
                endCommandBuffer(vk, *cmdBuffer);