soc: qcom: spm: Add CPU data for MSM8909

Given the lack of public documentation for the SPM, the configuration
data is taken without modification from Qualcomm's msm-3.10 release [1].
It is pretty much identical to the one for MSM8916, except that 0x3B is
missing in the sequence for standalone power collapse for some reason.

[1]: https://git.codelinaro.org/clo/la/kernel/msm-3.10/-/blob/LA.BR.1.2.3-00910-8x09.0/arch/arm/boot/dts/qcom/msm8909-pm8909-pm.dtsi

Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220705143523.3390944-7-stephan.gerhold@kernkonzept.com

diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
index f831420..484b42b 100644 (file)
--- a/drivers/soc/qcom/spm.c
+++ b/drivers/soc/qcom/spm.c
@@ -74,6 +74,18 @@ static const u16 spm_reg_offset_v3_0[SPM_REG_NR] = {
        [SPM_REG_SEQ_ENTRY]     = 0x400,
 };
 
+/* SPM register data for 8909 */
+static const struct spm_reg_data spm_reg_8909_cpu = {
+       .reg_offset = spm_reg_offset_v3_0,
+       .spm_cfg = 0x1,
+       .spm_dly = 0x3C102800,
+       .seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90,
+               0x5B, 0x60, 0x03, 0x60, 0x76, 0x76, 0x0B, 0x94, 0x5B, 0x80,
+               0x10, 0x26, 0x30, 0x0F },
+       .start_index[PM_SLEEP_MODE_STBY] = 0,
+       .start_index[PM_SLEEP_MODE_SPC] = 5,
+};
+
 /* SPM register data for 8916 */
 static const struct spm_reg_data spm_reg_8916_cpu = {
        .reg_offset = spm_reg_offset_v3_0,
@@ -195,6 +207,8 @@ static const struct of_device_id spm_match_table[] = {
          .data = &spm_reg_660_silver_l2 },
        { .compatible = "qcom,msm8226-saw2-v2.1-cpu",
          .data = &spm_reg_8226_cpu },
+       { .compatible = "qcom,msm8909-saw2-v3.0-cpu",
+         .data = &spm_reg_8909_cpu },
        { .compatible = "qcom,msm8916-saw2-v3.0-cpu",
          .data = &spm_reg_8916_cpu },
        { .compatible = "qcom,msm8974-saw2-v2.1-cpu",