DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
}
- /* Set data pid0 for all eps except for ep0 */
- doepctl.b.setd0pid = 1;
- for (i = 1; i <= dev_if->num_out_eps; i++) {
- dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
- }
-
- diepctl.b.setd0pid = 1;
- for (i = 1; i <= dev_if->num_in_eps; i++) {
- dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl, diepctl.d32);
- }
/* Flush the NP Tx FIFO */
dwc_otg_flush_tx_fifo(core_if, 0x10);
- /* Flush the NP Rx FIFO */
- dwc_otg_flush_rx_fifo(core_if);
/* Flush the Learning Queue */
resetctl.b.intknqflsh = 1;
DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);