drm/amdgpu/powerplay: Clean up errors in vega20_hwmgr.c

Fix the following errors reported by checkpatch:

ERROR: code indent should use tabs where possible
ERROR: space required before the open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'

Signed-off-by: Ran Sun <sunran001@208suo.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
index 4e19ccbdb8077e84a7fae095d540f2d85ebfb6ac..492ca33637d6f6eb494ee974fa659086da1e908f 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_hwmgr.c
@@ -1402,7 +1402,7 @@ static int vega20_od8_set_settings(
                        "Failed to export over drive table!",
                        return ret);
 
-       switch(index) {
+       switch (index) {
        case OD8_SETTING_GFXCLK_FMIN:
                od_table.GfxclkFmin = (uint16_t)value;
                break;
@@ -2360,7 +2360,7 @@ static int vega20_notify_smc_display_config_after_ps_adjustment(
                dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100;
                PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
                                PPSMC_MSG_SetHardMinByFreq,
-                               (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level,
+                               (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level,
                                NULL)),
                                "[SetHardMinFreq] Set hard min uclk failed!",
                                return ret);
@@ -3579,7 +3579,7 @@ static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
                dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
                PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
                                PPSMC_MSG_SetHardMinByFreq,
-                               (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level,
+                               (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level,
                                NULL)),
                                "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
                                return ret);
@@ -3605,7 +3605,7 @@ static int vega20_set_fclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr)
                dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
                PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
                                PPSMC_MSG_SetSoftMinByFreq,
-                               (PPCLK_FCLK << 16 ) | dpm_table->dpm_state.soft_min_level,
+                               (PPCLK_FCLK << 16) | dpm_table->dpm_state.soft_min_level,
                                NULL)),
                                "[SetFclkToHightestDpmLevel] Set soft min fclk failed!",
                                return ret);
@@ -3727,8 +3727,8 @@ static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
        uint32_t i, latency;
 
        disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
-                           !hwmgr->display_config->multi_monitor_in_sync) ||
-                            vblank_too_short;
+                               !hwmgr->display_config->multi_monitor_in_sync) ||
+                               vblank_too_short;
        latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
 
        /* gfxclk */