riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT

RISCV_NONSTANDARD_CACHE_OPS is also used for the pmem cache maintenance
helpers, which are built into the kernel unconditionally.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231018052654.50074-2-hch@lst.de
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index d607ab0f7c6dafa4f754f34a910ef66464e5a06d..0ac0b538379718f1464fb28fc59debcaf964595a 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -277,7 +277,6 @@ config RISCV_DMA_NONCOHERENT
 
 config RISCV_NONSTANDARD_CACHE_OPS
        bool
-       depends on RISCV_DMA_NONCOHERENT
        help
          This enables function pointer support for non-standard noncoherent
          systems to handle cache management.

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index a57677f908f3ba3c134fb97e7c1eecd7159d8f0c..d6e5e3abaad8afde8f2f0a852f2408b4e1c5c4ac 100644 (file)
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -3,7 +3,7 @@ menu "Cache Drivers"
 
 config AX45MP_L2_CACHE
        bool "Andes Technology AX45MP L2 Cache controller"
-       depends on RISCV_DMA_NONCOHERENT
+       depends on RISCV
        select RISCV_NONSTANDARD_CACHE_OPS
        help
          Support for the L2 cache controller on Andes Technology AX45MP platforms.