The 24k wants more watch and srsmap registers.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2849 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index e0f03ed..9cddc17 100644 (file)
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -216,8 +216,8 @@ struct CPUMIPSState {
     int32_t CP0_Config6;
     int32_t CP0_Config7;
     target_ulong CP0_LLAddr;
-    target_ulong CP0_WatchLo;
-    int32_t CP0_WatchHi;
+    target_ulong CP0_WatchLo[8];
+    int32_t CP0_WatchHi[8];
     target_ulong CP0_XContext;
     int32_t CP0_Framemask;
     int32_t CP0_Debug;

diff --git a/target-mips/helper.c b/target-mips/helper.c
index 306ddf0..2dfaffc 100644 (file)
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -381,7 +381,7 @@ void do_interrupt (CPUState *env)
         break;
     case EXCP_SRESET:
         env->CP0_Status |= (1 << CP0St_SR);
-        env->CP0_WatchLo = 0;
+        memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
         goto set_error_EPC;
     case EXCP_NMI:
         env->CP0_Status |= (1 << CP0St_NMI);

diff --git a/target-mips/op.c b/target-mips/op.c
index 8f5b11c..8f67041 100644 (file)
--- a/target-mips/op.c
+++ b/target-mips/op.c
@@ -1171,15 +1171,15 @@ void op_mfc0_lladdr (void)
     RETURN();
 }
 
-void op_mfc0_watchlo0 (void)
+void op_mfc0_watchlo (void)
 {
-    T0 = (int32_t)env->CP0_WatchLo;
+    T0 = (int32_t)env->CP0_WatchLo[PARAM1];
     RETURN();
 }
 
-void op_mfc0_watchhi0 (void)
+void op_mfc0_watchhi (void)
 {
-    T0 = env->CP0_WatchHi;
+    T0 = env->CP0_WatchHi[PARAM1];
     RETURN();
 }
 
@@ -1423,18 +1423,18 @@ void op_mtc0_config2 (void)
     RETURN();
 }
 
-void op_mtc0_watchlo0 (void)
+void op_mtc0_watchlo (void)
 {
     /* Watch exceptions for instructions, data loads, data stores
        not implemented. */
-    env->CP0_WatchLo = (T0 & ~0x7);
+    env->CP0_WatchLo[PARAM1] = (T0 & ~0x7);
     RETURN();
 }
 
-void op_mtc0_watchhi0 (void)
+void op_mtc0_watchhi (void)
 {
-    env->CP0_WatchHi = (T0 & 0x40FF0FF8);
-    env->CP0_WatchHi &= ~(env->CP0_WatchHi & T0 & 0x7);
+    env->CP0_WatchHi[PARAM1] = (T0 & 0x40FF0FF8);
+    env->CP0_WatchHi[PARAM1] &= ~(env->CP0_WatchHi[PARAM1] & T0 & 0x7);
     RETURN();
 }
 
@@ -1551,9 +1551,9 @@ void op_dmfc0_lladdr (void)
     RETURN();
 }
 
-void op_dmfc0_watchlo0 (void)
+void op_dmfc0_watchlo (void)
 {
-    T0 = env->CP0_WatchLo;
+    T0 = env->CP0_WatchLo[PARAM1];
     RETURN();
 }
 

diff --git a/target-mips/translate.c b/target-mips/translate.c
index ddf560d..4da5b7b 100644 (file)
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -2035,9 +2035,9 @@ static void gen_mfc0 (DisasContext *ctx, int reg, int sel)
             rn = "SRSCtl";
             break;
         case 3:
-//            gen_op_mfc0_srsmap(); /* shadow registers */
+            gen_op_mfc0_srsmap();
             rn = "SRSMap";
-//            break;
+            break;
         default:
             goto die;
        }
@@ -2120,76 +2120,20 @@ static void gen_mfc0 (DisasContext *ctx, int reg, int sel)
         break;
     case 18:
         switch (sel) {
-        case 0:
-            gen_op_mfc0_watchlo0();
+        case 0 ... 7:
+            gen_op_mfc0_watchlo(sel);
             rn = "WatchLo";
             break;
-        case 1:
-//            gen_op_mfc0_watchlo1();
-            rn = "WatchLo1";
-//            break;
-        case 2:
-//            gen_op_mfc0_watchlo2();
-            rn = "WatchLo2";
-//            break;
-        case 3:
-//            gen_op_mfc0_watchlo3();
-            rn = "WatchLo3";
-//            break;
-        case 4:
-//            gen_op_mfc0_watchlo4();
-            rn = "WatchLo4";
-//            break;
-        case 5:
-//            gen_op_mfc0_watchlo5();
-            rn = "WatchLo5";
-//            break;
-        case 6:
-//            gen_op_mfc0_watchlo6();
-            rn = "WatchLo6";
-//            break;
-        case 7:
-//            gen_op_mfc0_watchlo7();
-            rn = "WatchLo7";
-//            break;
         default:
             goto die;
         }
         break;
     case 19:
         switch (sel) {
-        case 0:
-            gen_op_mfc0_watchhi0();
+        case 0 ...7:
+            gen_op_mfc0_watchhi(sel);
             rn = "WatchHi";
             break;
-        case 1:
-//            gen_op_mfc0_watchhi1();
-            rn = "WatchHi1";
-//            break;
-        case 2:
-//            gen_op_mfc0_watchhi2();
-            rn = "WatchHi2";
-//            break;
-        case 3:
-//            gen_op_mfc0_watchhi3();
-            rn = "WatchHi3";
-//            break;
-        case 4:
-//            gen_op_mfc0_watchhi4();
-            rn = "WatchHi4";
-//            break;
-        case 5:
-//            gen_op_mfc0_watchhi5();
-            rn = "WatchHi5";
-//            break;
-        case 6:
-//            gen_op_mfc0_watchhi6();
-            rn = "WatchHi6";
-//            break;
-        case 7:
-//            gen_op_mfc0_watchhi7();
-            rn = "WatchHi7";
-//            break;
         default:
             goto die;
         }
@@ -2625,9 +2569,9 @@ static void gen_mtc0 (DisasContext *ctx, int reg, int sel)
             rn = "SRSCtl";
             break;
         case 3:
-//            gen_op_mtc0_srsmap(); /* shadow registers */
+            gen_op_mtc0_srsmap();
             rn = "SRSMap";
-//            break;
+            break;
         default:
             goto die;
         }
@@ -2719,76 +2663,20 @@ static void gen_mtc0 (DisasContext *ctx, int reg, int sel)
         break;
     case 18:
         switch (sel) {
-        case 0:
-            gen_op_mtc0_watchlo0();
+        case 0 ... 7:
+            gen_op_mtc0_watchlo(sel);
             rn = "WatchLo";
             break;
-        case 1:
-//            gen_op_mtc0_watchlo1();
-            rn = "WatchLo1";
-//            break;
-        case 2:
-//            gen_op_mtc0_watchlo2();
-            rn = "WatchLo2";
-//            break;
-        case 3:
-//            gen_op_mtc0_watchlo3();
-            rn = "WatchLo3";
-//            break;
-        case 4:
-//            gen_op_mtc0_watchlo4();
-            rn = "WatchLo4";
-//            break;
-        case 5:
-//            gen_op_mtc0_watchlo5();
-            rn = "WatchLo5";
-//            break;
-        case 6:
-//            gen_op_mtc0_watchlo6();
-            rn = "WatchLo6";
-//            break;
-        case 7:
-//            gen_op_mtc0_watchlo7();
-            rn = "WatchLo7";
-//            break;
         default:
             goto die;
         }
         break;
     case 19:
         switch (sel) {
-        case 0:
-            gen_op_mtc0_watchhi0();
+        case 0 ... 7:
+            gen_op_mtc0_watchhi(sel);
             rn = "WatchHi";
             break;
-        case 1:
-//            gen_op_mtc0_watchhi1();
-            rn = "WatchHi1";
-//            break;
-        case 2:
-//            gen_op_mtc0_watchhi2();
-            rn = "WatchHi2";
-//            break;
-        case 3:
-//            gen_op_mtc0_watchhi3();
-            rn = "WatchHi3";
-//            break;
-        case 4:
-//            gen_op_mtc0_watchhi4();
-            rn = "WatchHi4";
-//            break;
-        case 5:
-//            gen_op_mtc0_watchhi5();
-            rn = "WatchHi5";
-//            break;
-        case 6:
-//            gen_op_mtc0_watchhi6();
-            rn = "WatchHi6";
-//            break;
-        case 7:
-//            gen_op_mtc0_watchhi7();
-            rn = "WatchHi7";
-//            break;
         default:
             goto die;
         }
@@ -3309,76 +3197,20 @@ static void gen_dmfc0 (DisasContext *ctx, int reg, int sel)
         break;
     case 18:
         switch (sel) {
-        case 0:
-            gen_op_dmfc0_watchlo0();
+        case 0 ... 7:
+            gen_op_dmfc0_watchlo(sel);
             rn = "WatchLo";
             break;
-        case 1:
-//            gen_op_dmfc0_watchlo1();
-            rn = "WatchLo1";
-//            break;
-        case 2:
-//            gen_op_dmfc0_watchlo2();
-            rn = "WatchLo2";
-//            break;
-        case 3:
-//            gen_op_dmfc0_watchlo3();
-            rn = "WatchLo3";
-//            break;
-        case 4:
-//            gen_op_dmfc0_watchlo4();
-            rn = "WatchLo4";
-//            break;
-        case 5:
-//            gen_op_dmfc0_watchlo5();
-            rn = "WatchLo5";
-//            break;
-        case 6:
-//            gen_op_dmfc0_watchlo6();
-            rn = "WatchLo6";
-//            break;
-        case 7:
-//            gen_op_dmfc0_watchlo7();
-            rn = "WatchLo7";
-//            break;
         default:
             goto die;
         }
         break;
     case 19:
         switch (sel) {
-        case 0:
-            gen_op_mfc0_watchhi0();
+        case 0 ... 7:
+            gen_op_mfc0_watchhi(sel);
             rn = "WatchHi";
             break;
-        case 1:
-//            gen_op_mfc0_watchhi1();
-            rn = "WatchHi1";
-//            break;
-        case 2:
-//            gen_op_mfc0_watchhi2();
-            rn = "WatchHi2";
-//            break;
-        case 3:
-//            gen_op_mfc0_watchhi3();
-            rn = "WatchHi3";
-//            break;
-        case 4:
-//            gen_op_mfc0_watchhi4();
-            rn = "WatchHi4";
-//            break;
-        case 5:
-//            gen_op_mfc0_watchhi5();
-            rn = "WatchHi5";
-//            break;
-        case 6:
-//            gen_op_mfc0_watchhi6();
-            rn = "WatchHi6";
-//            break;
-        case 7:
-//            gen_op_mfc0_watchhi7();
-            rn = "WatchHi7";
-//            break;
         default:
             goto die;
         }
@@ -3814,7 +3646,7 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
             rn = "SRSCtl";
             break;
         case 3:
-            gen_op_mtc0_srsmap(); /* shadow registers */
+            gen_op_mtc0_srsmap();
             rn = "SRSMap";
             break;
         default:
@@ -3899,76 +3731,20 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel)
         break;
     case 18:
         switch (sel) {
-        case 0:
-            gen_op_mtc0_watchlo0();
+        case 0 ... 7:
+            gen_op_mtc0_watchlo(sel);
             rn = "WatchLo";
             break;
-        case 1:
-//            gen_op_mtc0_watchlo1();
-            rn = "WatchLo1";
-//            break;
-        case 2:
-//            gen_op_mtc0_watchlo2();
-            rn = "WatchLo2";
-//            break;
-        case 3:
-//            gen_op_mtc0_watchlo3();
-            rn = "WatchLo3";
-//            break;
-        case 4:
-//            gen_op_mtc0_watchlo4();
-            rn = "WatchLo4";
-//            break;
-        case 5:
-//            gen_op_mtc0_watchlo5();
-            rn = "WatchLo5";
-//            break;
-        case 6:
-//            gen_op_mtc0_watchlo6();
-            rn = "WatchLo6";
-//            break;
-        case 7:
-//            gen_op_mtc0_watchlo7();
-            rn = "WatchLo7";
-//            break;
         default:
             goto die;
         }
         break;
     case 19:
         switch (sel) {
-        case 0:
-            gen_op_mtc0_watchhi0();
+        case 0 ... 7:
+            gen_op_mtc0_watchhi(sel);
             rn = "WatchHi";
             break;
-        case 1:
-//            gen_op_mtc0_watchhi1();
-            rn = "WatchHi1";
-//            break;
-        case 2:
-//            gen_op_mtc0_watchhi2();
-            rn = "WatchHi2";
-//            break;
-        case 3:
-//            gen_op_mtc0_watchhi3();
-            rn = "WatchHi3";
-//            break;
-        case 4:
-//            gen_op_mtc0_watchhi4();
-            rn = "WatchHi4";
-//            break;
-        case 5:
-//            gen_op_mtc0_watchhi5();
-            rn = "WatchHi5";
-//            break;
-        case 6:
-//            gen_op_mtc0_watchhi6();
-            rn = "WatchHi6";
-//            break;
-        case 7:
-//            gen_op_mtc0_watchhi7();
-            rn = "WatchHi7";
-//            break;
         default:
             goto die;
         }
@@ -6269,8 +6045,16 @@ void cpu_reset (CPUMIPSState *env)
     /* vectored interrupts not implemented, timer on int 7,
        no performance counters. */
     env->CP0_IntCtl = 0xe0000000;
-    env->CP0_WatchLo = 0;
-    env->CP0_WatchHi = 0;
+    {
+        int i;
+
+        for (i = 0; i < 7; i++) {
+            env->CP0_WatchLo[i] = 0;
+            env->CP0_WatchHi[i] = 0x80000000;
+        }
+        env->CP0_WatchLo[7] = 0;
+        env->CP0_WatchHi[7] = 0;
+    }
     /* Count register increments in debug mode, EJTAG version 1 */
     env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
 #endif