drm/amdgpu: enable 4 level page table on raven (v3)

v1: enable 4 level-page table on raven
v2: add back legacy 2 level page table on raven
v3: set num_level in initial switch statement

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 175ba5f..c6394ea 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -537,10 +537,20 @@ static int gmc_v9_0_sw_init(void *handle)
 
        spin_lock_init(&adev->mc.invalidate_lock);
 
-       if (adev->flags & AMD_IS_APU) {
+       switch (adev->asic_type) {
+       case CHIP_RAVEN:
                adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
-               amdgpu_vm_adjust_size(adev, 64);
-       } else {
+               if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
+                       adev->vm_manager.vm_size = 1U << 18;
+                       adev->vm_manager.block_size = 9;
+                       adev->vm_manager.num_level = 3;
+               } else {
+                       /* vm_size is 64GB for legacy 2-level page support*/
+                       amdgpu_vm_adjust_size(adev, 64);
+                       adev->vm_manager.num_level = 1;
+               }
+               break;
+       case CHIP_VEGA10:
                /* XXX Don't know how to get VRAM type yet. */
                adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM;
                /*
@@ -550,11 +560,16 @@ static int gmc_v9_0_sw_init(void *handle)
                 */
                adev->vm_manager.vm_size = 1U << 18;
                adev->vm_manager.block_size = 9;
-               DRM_INFO("vm size is %llu GB, block size is %u-bit\n",
-                               adev->vm_manager.vm_size,
-                               adev->vm_manager.block_size);
+               adev->vm_manager.num_level = 3;
+               break;
+       default:
+               break;
        }
 
+       DRM_INFO("vm size is %llu GB, block size is %u-bit\n",
+                       adev->vm_manager.vm_size,
+                       adev->vm_manager.block_size);
+
        /* This interrupt is VMC page fault.*/
        r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_VMC, 0,
                                &adev->mc.vm_fault);
@@ -619,11 +634,6 @@ static int gmc_v9_0_sw_init(void *handle)
        adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
        adev->vm_manager.id_mgr[AMDGPU_MMHUB].num_ids = AMDGPU_NUM_OF_VMIDS;
 
-       /* TODO: fix num_level for APU when updating vm size and block size */
-       if (adev->flags & AMD_IS_APU)
-               adev->vm_manager.num_level = 1;
-       else
-               adev->vm_manager.num_level = 3;
        amdgpu_vm_manager_init(adev);
 
        return 0;