FlowControl equ $
FlowOutput resb 1 ; Outputs to assert for serial flow
FlowInput resb 1 ; Input bits for serial flow
+FlowIgnore resb 1 ; Ignore input unless these bits set
RetryCount resb 1 ; Used for disk access retries
KbdFlags resb 1 ; Check for keyboard escapes
LoadFlags resb 1 ; Loadflags from kernel
call ungetc
call getint ; Hardware flow control?
jnc .valid_flow
- xor bl,bl ; Default -> no flow control
+ xor bx,bx ; Default -> no flow control
.valid_flow:
+ and bh,0Fh ; FlowIgnore
+ shl bh,4
+ mov [FlowIgnore],bh
mov bh,bl
and bx,0F003h ; Valid bits
mov [FlowControl],bx
add dx,byte 3 ; DX -> MCR
in al,dx
- mov ah,[FlowOutput] ; DTR and RTS control
- or al,ah ; Assert bits
+ or al,[FlowOutput] ; Assert bits
call slow_out
; Show some life
add dx,byte 5 ; DX -> LSR
in al,dx
test al,1 ; ZF = 0 if data pending
+ jz .done
+ inc dx ; DX -> MSR
+ mov ah,[FlowIgnore] ; Required status bits
+ in al,dx
+ and al,ah
+ cmp al,ah
+ setne al
+ dec al ; Set ZF = 0 if equal
.done: popad
ret
mov bx,[SerialPort]
and bx,bx
jz .again
- lea dx,[bx+5] ; Serial status register
+ lea dx,[bx+5] ; DX -> LSR
in al,dx
test al,1
jz .again
+ inc dx ; DX -> MSR
+ mov ah,[FlowIgnore]
+ in al,dx
+ and al,ah
+ cmp al,ah
+ jne .again
.serial: xor ah,ah ; Avoid confusion
xchg dx,bx ; Data port
in al,dx
FlowControl equ $
FlowOutput resb 1 ; Outputs to assert for serial flow
FlowInput resb 1 ; Input bits for serial flow
+FlowIgnore resb 1 ; Ignore input unless these bits set
RetryCount resb 1 ; Used for disk access retries
KbdFlags resb 1 ; Check for keyboard escapes
LoadFlags resb 1 ; Loadflags from kernel
call ungetc
call getint ; Hardware flow control?
jnc .valid_flow
- xor bl,bl ; Default -> no flow control
+ xor bx,bx ; Default -> no flow control
.valid_flow:
+ and bh,0Fh ; FlowIgnore
+ shl bh,4
+ mov [FlowIgnore],bh
mov bh,bl
and bx,0F003h ; Valid bits
mov [FlowControl],bx
add dx,byte 3 ; DX -> MCR
in al,dx
- mov ah,[FlowOutput] ; DTR and RTS control
- or al,ah ; Assert bits
+ or al,[FlowOutput] ; Assert bits
call slow_out
; Show some life
add dx,byte 5 ; DX -> LSR
in al,dx
test al,1 ; ZF = 0 if data pending
+ jz .done
+ inc dx ; DX -> MSR
+ mov ah,[FlowIgnore] ; Required status bits
+ in al,dx
+ and al,ah
+ cmp al,ah
+ setne al
+ dec al ; Set ZF = 0 if equal
.done: popad
ret
mov bx,[SerialPort]
and bx,bx
jz .again
- lea dx,[bx+5] ; Serial status register
+ lea dx,[bx+5] ; DX -> LSR
in al,dx
test al,1
jz .again
+ inc dx ; DX -> MSR
+ mov ah,[FlowIgnore]
+ in al,dx
+ and al,ah
+ cmp al,ah
+ jne .again
.serial: xor ah,ah ; Avoid confusion
xchg dx,bx ; Data port
in al,dx
FlowControl equ $
FlowOutput resb 1 ; Outputs to assert for serial flow
FlowInput resb 1 ; Input bits for serial flow
+FlowIgnore resb 1 ; Ignore input unless these bits set
RetryCount resb 1 ; Used for disk access retries
KbdFlags resb 1 ; Check for keyboard escapes
LoadFlags resb 1 ; Loadflags from kernel
call ungetc
call getint ; Hardware flow control?
jnc .valid_flow
- xor bl,bl ; Default -> no flow control
+ xor bx,bx ; Default -> no flow control
.valid_flow:
+ and bh,0Fh ; FlowIgnore
+ shl bh,4
+ mov [FlowIgnore],bh
mov bh,bl
and bx,0F003h ; Valid bits
mov [FlowControl],bx
add dx,byte 3 ; DX -> MCR
in al,dx
- mov ah,[FlowOutput] ; DTR and RTS control
- or al,ah ; Assert bits
+ or al,[FlowOutput] ; Assert bits
call slow_out
; Show some life
add dx,byte 5 ; DX -> LSR
in al,dx
test al,1 ; ZF = 0 if data pending
+ jz .done
+ inc dx ; DX -> MSR
+ mov ah,[FlowIgnore] ; Required status bits
+ in al,dx
+ and al,ah
+ cmp al,ah
+ setne al
+ dec al ; Set ZF = 0 if equal
.done: popad
ret
mov bx,[SerialPort]
and bx,bx
jz .again
- lea dx,[bx+5] ; Serial status register
+ lea dx,[bx+5] ; DX -> LSR
in al,dx
test al,1
jz .again
+ inc dx ; DX -> MSR
+ mov ah,[FlowIgnore]
+ in al,dx
+ and al,ah
+ cmp al,ah
+ jne .again
.serial: xor ah,ah ; Avoid confusion
xchg dx,bx ; Data port
in al,dx
bits, no parity, 1 stop bit.
"flowcontrol" is a combination of the following bits:
- 1 - Assert DTR
- 2 - Assert RTS
- 16 - Wait for CTS assertion
- 32 - Wait for DSR assertion
- 64 - Wait for RI assertion
- 128 - Wait for DCD assertion
+ 0x001 - Assert DTR
+ 0x002 - Assert RTS
+ 0x010 - Wait for CTS assertion
+ 0x020 - Wait for DSR assertion
+ 0x040 - Wait for RI assertion
+ 0x080 - Wait for DCD assertion
+ 0x100 - Ignore input unless CTS asserted
+ 0x200 - Ignore input unless DSR asserted
+ 0x400 - Ignore input unless RI asserted
+ 0x800 - Ignore input unless DCD asserted
+
+ All other bits are reserved.
Typical values are:
- 0 - No flow control (default)
- 19 - RTS/CTS flow control
- 35 - DTR/DSR flow control
- 131 - DTR/DCD flow control
+ 0 - No flow control (default)
+ 0x013 - RTS/CTS flow control
+ 0x813 - RTS/CTS flow control, modem input
+ 0x023 - DTR/DSR flow control
+ 0x083 - DTR/DCD flow control
- All other values are reserved.
-
- For this directive to be guaranteed to work properly, it
+ For the SERIAL directive to be guaranteed to work properly, it
should be the first directive in the configuration file.
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