return regs;
}
-/* traverse all cores to find and clear source of serror */
-static void sb_serr_clear(si_info_t *sii)
-{
- sbconfig_t *sb;
- uint origidx;
- uint i, intr_val = 0;
- void *corereg = NULL;
-
- INTR_OFF(sii, intr_val);
- origidx = si_coreidx(&sii->pub);
-
- for (i = 0; i < sii->numcores; i++) {
- corereg = sb_setcoreidx(&sii->pub, i);
- if (NULL != corereg) {
- sb = REGS2SB(corereg);
- if ((R_SBREG(sii, &sb->sbtmstatehigh)) & SBTMH_SERR) {
- AND_SBREG(sii, &sb->sbtmstatehigh, ~SBTMH_SERR);
- SI_ERROR(("sb_serr_clear: SError core 0x%x\n",
- sb_coreid(&sii->pub)));
- }
- }
- }
-
- sb_setcoreidx(&sii->pub, origidx);
- INTR_RESTORE(sii, intr_val);
-}
-
-/*
- * Check if any inband, outband or timeout errors has happened and clear them.
- * Must be called with chip clk on !
- */
-bool sb_taclear(si_t *sih, bool details)
-{
- si_info_t *sii;
- sbconfig_t *sb;
- uint origidx;
- uint intr_val = 0;
- bool rc = false;
- u32 inband = 0, serror = 0, timeout = 0;
- void *corereg = NULL;
- volatile u32 imstate, tmstate;
-
- sii = SI_INFO(sih);
-
- if ((sii->pub.bustype == SDIO_BUS) ||
- (sii->pub.bustype == SPI_BUS)) {
-
- INTR_OFF(sii, intr_val);
- origidx = si_coreidx(sih);
-
- corereg = si_setcore(sih, PCMCIA_CORE_ID, 0);
- if (NULL == corereg)
- corereg = si_setcore(sih, SDIOD_CORE_ID, 0);
- if (NULL != corereg) {
- sb = REGS2SB(corereg);
-
- imstate = R_SBREG(sii, &sb->sbimstate);
- if ((imstate != 0xffffffff)
- && (imstate & (SBIM_IBE | SBIM_TO))) {
- AND_SBREG(sii, &sb->sbimstate,
- ~(SBIM_IBE | SBIM_TO));
- /* inband = imstate & SBIM_IBE; cmd error */
- timeout = imstate & SBIM_TO;
- }
- tmstate = R_SBREG(sii, &sb->sbtmstatehigh);
- if ((tmstate != 0xffffffff)
- && (tmstate & SBTMH_INT_STATUS)) {
- sb_serr_clear(sii);
- serror = 1;
- OR_SBREG(sii, &sb->sbtmstatelow, SBTML_INT_ACK);
- AND_SBREG(sii, &sb->sbtmstatelow,
- ~SBTML_INT_ACK);
- }
- }
-
- sb_setcoreidx(sih, origidx);
- INTR_RESTORE(sii, intr_val);
- }
-
- if (inband | timeout | serror) {
- rc = true;
- SI_ERROR(("sb_taclear: inband 0x%x, serror 0x%x, timeout "
- "0x%x!\n", inband, serror, timeout));
- }
-
- return rc;
-}
-
void sb_core_disable(si_t *sih, u32 bits)
{
si_info_t *sii;
dummy = R_SBREG(sii, &sb->sbtmstatelow);
udelay(1);
}
-
-u32 sb_base(u32 admatch)
-{
- u32 base;
- uint type;
-
- type = admatch & SBAM_TYPE_MASK;
- ASSERT(type < 3);
-
- base = 0;
-
- if (type == 0) {
- base = admatch & SBAM_BASE0_MASK;
- } else if (type == 1) {
- ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
- base = admatch & SBAM_BASE1_MASK;
- } else if (type == 2) {
- ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
- base = admatch & SBAM_BASE2_MASK;
- }
-
- return base;
-}