uint64_t start_blk = 0, part_blk = 0;
loff_t offset;
int phys_erase_shift, error = 0;
+ int plane_num_shift = 0;
if (!mtd->erasesize)
return -EINVAL;
phys_erase_shift = fls(mtd->erasesize) - 1;
+
+ if (!aml_chip->plane_num)
+ return -EINVAL;
+ plane_num_shift = fls(aml_chip->plane_num) - 1;
#endif
parts = plat->platform_nand_data.chip.partitions;
return -ENOMEM;
}
if (nand_boot_flag)
- adjust_offset =
- (loff_t)(1024 * mtd->writesize /
- aml_chip->plane_num);
+ adjust_offset = (1024 * ((loff_t)mtd->writesize) >>
+ plane_num_shift);
bl_mode = aml_chip->bl_mode;
if (bl_mode == NAND_FIPMODE_DISCRETE) {
/* descrete bootloader mode */
struct nand_chip *chip = mtd->priv;
loff_t ofs;
- ofs = (loff_t)(page << chip->page_shift);
+ ofs = ((loff_t)page << chip->page_shift);
if (chip->block_bad(mtd, ofs))
return -1;
read_page = page;
read_page++;
READ_BAD_BLOCK:
- ofs = (uint64_t)(read_page << chip->page_shift);
+ ofs = ((uint64_t)read_page << chip->page_shift);
tmp = ofs;
div_u64_rem(tmp, mtd->erasesize, &remainder);
if (!remainder) {
write_page++;
WRITE_BAD_BLOCK:
- ofs = (uint64_t)(write_page << chip->page_shift);
+ ofs = ((uint64_t)write_page << chip->page_shift);
tmp = ofs;
div_u64_rem(tmp, mtd->erasesize, &remainder);
if (!remainder) {
aml_oob_ops.ooboffs = 0;/*fixme! all layout offs is zero*/
aml_oob_ops.datbuf = data_buf;
aml_oob_ops.oobbuf = oob_buf;
- op_add = (loff_t)(next_msb_page*mtd->writesize);
+ op_add = ((loff_t)next_msb_page*mtd->writesize);
mtd->_write_oob(mtd, op_add, &aml_oob_ops);
pr_info("Eneter 1y nm SLC mode ,must fill 0xff data into %d\n",
next_msb_page);
aml_oob_ops.ooboffs = 0;/*fixme! all layout offs is zero*/
aml_oob_ops.datbuf = buf;
aml_oob_ops.oobbuf = oob_buf;
- op_add = (loff_t)(op_page_add*mtd->writesize);
+ op_add = ((loff_t)op_page_add*mtd->writesize);
error = mtd->_write_oob(mtd, op_add, &aml_oob_ops);
pr_info("Eneter 1y nm SLC mode ,write systerm data into %d\n",
op_page_add);
struct aml_nand_platform *plat = aml_chip->platform;
unsigned char *data_buf;
int32_t read_cnt, page, pages_per_blk;
- loff_t addr, offset;
+ loff_t addr;
int start_blk = 0, total_blk = 0, bad_blk_cnt = 0, phys_erase_shift;
int realpage, col0_data = 0, col0_oob = 0, valid_page_num = 1;
int col_data_sandisk[6] = {0}, bad_sandisk_flag = 0;
int i, j;
+ uint32_t offset;
if (!mtd->erasesize)
return -EINVAL;
memset(&aml_chip->nand_bbt_info->nand_bbt[0],
0, MAX_BAD_BLK_NUM);
if (nand_boot_flag)
- offset =
- (loff_t)(1024 * mtd->writesize / aml_chip->plane_num);
+ offset = (1024 * mtd->writesize /
+ aml_chip->plane_num);
else
offset = 0;
/* if (aml_chip->valid_chip[i]) { */
for (read_cnt = 0; read_cnt < 2; read_cnt++) {
if (aml_chip->mfr_type == NAND_MFR_SANDISK) {
- addr = offset + read_cnt*mtd->writesize;
+ addr = (loff_t)offset + read_cnt*mtd->writesize;
} else
- addr = offset +
+ addr = (loff_t)offset +
(pages_per_blk - 1) * read_cnt * mtd->writesize;
realpage = (int)(addr >> chip->page_shift);