arm64: dts: qcom: qdu1000: Supply clock from cpufreq node to CPUs

Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-7-manivannan.sadhasivam@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
index f234159d2060eb02865ece141a8ea02f1798eaba..98a859ad5229b279c24542cd9b42b269419551d6 100644 (file)
--- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@ -27,6 +27,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a55";
                        reg = <0x0 0x0>;
+                       clocks = <&cpufreq_hw 0>;
                        enable-method = "psci";
                        power-domains = <&CPU_PD0>;
                        power-domain-names = "psci";
@@ -45,6 +46,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a55";
                        reg = <0x0 0x100>;
+                       clocks = <&cpufreq_hw 0>;
                        enable-method = "psci";
                        power-domains = <&CPU_PD1>;
                        power-domain-names = "psci";
@@ -60,6 +62,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a55";
                        reg = <0x0 0x200>;
+                       clocks = <&cpufreq_hw 0>;
                        enable-method = "psci";
                        power-domains = <&CPU_PD2>;
                        power-domain-names = "psci";
@@ -75,6 +78,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a55";
                        reg = <0x0 0x300>;
+                       clocks = <&cpufreq_hw 0>;
                        enable-method = "psci";
                        power-domains = <&CPU_PD3>;
                        power-domain-names = "psci";
@@ -1312,6 +1316,7 @@
                        clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
                        clock-names = "xo", "alternate";
                        #freq-domain-cells = <1>;
+                       #clock-cells = <1>;
                };
 
                gem_noc: interconnect@19100000 {