When order is equal to __riscv_xlen, the shift operation will not perform
any operation, which will cause reg->base & (BIT(reg->order) - 1) to always
be 0, and the condition has not been established.
This patch fixes this bug.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
if (reg->order < 3 || __riscv_xlen < reg->order)
return FALSE;
+ if (reg->order == __riscv_xlen && reg->base != 0)
+ return FALSE;
+
if (reg->base & (BIT(reg->order) - 1))
return FALSE;