#define I2C_BASE1 0x44E0B000
#define I2C_BASE2 0x4802A000
#define I2C_BASE3 0x4819C000
-#define CONFIG_SYS_I2C_BUS_MAX 3
#define I2C_DEFAULT_BASE I2C_BASE1
#ifndef _OMAP3_I2C_H_
#define _OMAP3_I2C_H_
-#define CONFIG_SYS_I2C_BUS_MAX 3
#define I2C_DEFAULT_BASE I2C_BASE1
struct i2c {
#ifndef _OMAP4_I2C_H_
#define _OMAP4_I2C_H_
-#define CONFIG_SYS_I2C_BUS_MAX 4
#define I2C_DEFAULT_BASE I2C_BASE1
struct i2c {
#ifndef _OMAP5_I2C_H_
#define _OMAP5_I2C_H_
-#define CONFIG_SYS_I2C_BUS_MAX 5
#define I2C_DEFAULT_BASE I2C_BASE1
struct i2c {
by the BPMP, and can only be accessed by the main CPU via IPC
requests to the BPMP. This driver covers the latter case.
+config SYS_I2C_BUS_MAX
+ int "Max I2C busses"
+ depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
+ default 2 if TI816X
+ default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
+ default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
+ default 5 if OMAP54XX
+ help
+ Define the maximum number of available I2C buses.
+
source "drivers/i2c/muxes/Kconfig"
endmenu
* I2C support
*/
#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_BUS_MAX 4
#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
#define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS
#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */
#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */
-#define CONFIG_SYS_I2C_BUS_MAX 3
/* EEPROM definitions */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2