haswell: fix 3DSTATE_PS to fill in number of samples.

The sample mask value must match what is set for 3DSTATE_SAMPLE_MASK,
through gen7_emit_invarient_states().

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

diff --git a/src/i965_defines.h b/src/i965_defines.h
index 3e64a5e..a9a5185 100755 (executable)
--- a/src/i965_defines.h
+++ b/src/i965_defines.h
@@ -236,6 +236,7 @@
 /* DW4 */
 # define GEN7_PS_MAX_THREADS_SHIFT_IVB                  24
 # define GEN7_PS_MAX_THREADS_SHIFT_HSW                  23
+# define GEN7_PS_SAMPLE_MASK_SHIFT_HSW                  12
 # define GEN7_PS_PUSH_CONSTANT_ENABLE                   (1 << 11)
 # define GEN7_PS_ATTRIBUTE_ENABLE                       (1 << 10)
 # define GEN7_PS_OMASK_TO_RENDER_TARGET                 (1 << 9)

diff --git a/src/i965_render.c b/src/i965_render.c
index f9d2ac7..cb10af5 100644 (file)
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -2731,9 +2731,11 @@ gen7_emit_wm_state(VADriverContextP ctx, int kernel)
     struct intel_batchbuffer *batch = i965->batch;
     struct i965_render_state *render_state = &i965->render_state;
     unsigned int max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_IVB;
+    unsigned int num_samples = 0;
 
     if (IS_HASWELL(i965->intel.device_id)) {
         max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_HSW;
+        num_samples = 1 << GEN7_PS_SAMPLE_MASK_SHIFT_HSW;
     }
 
     BEGIN_BATCH(batch, 3);
@@ -2768,7 +2770,7 @@ gen7_emit_wm_state(VADriverContextP ctx, int kernel)
               (5 << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
     OUT_BATCH(batch, 0); /* scratch space base offset */
     OUT_BATCH(batch, 
-              ((86 - 1) << max_threads_shift) |
+              ((86 - 1) << max_threads_shift) | num_samples |
               GEN7_PS_PUSH_CONSTANT_ENABLE |
               GEN7_PS_ATTRIBUTE_ENABLE |
               GEN7_PS_16_DISPATCH_ENABLE);