clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset()

[ Upstream commit 5f9e29b9159a41fcf6733c3b59fa46a90ce3ae20 ]

Code in rzg2l_cpg_reset() is equivalent with the combined code of
rzg2l_cpg_assert() and rzg2l_cpg_deassert(). There is no need to have
different versions thus re-use rzg2l_cpg_assert() and rzg2l_cpg_deassert().

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231120070024.4079344-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Stable-dep-of: da235d2fac21 ("clk: renesas: rzg2l: Check reset monitor registers")
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 3f01620..8303282 100644 (file)
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -1105,29 +1105,6 @@ fail:
 
 #define rcdev_to_priv(x)       container_of(x, struct rzg2l_cpg_priv, rcdev)
 
-static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
-                          unsigned long id)
-{
-       struct rzg2l_cpg_priv *priv = rcdev_to_priv(rcdev);
-       const struct rzg2l_cpg_info *info = priv->info;
-       unsigned int reg = info->resets[id].off;
-       u32 dis = BIT(info->resets[id].bit);
-       u32 we = dis << 16;
-
-       dev_dbg(rcdev->dev, "reset id:%ld offset:0x%x\n", id, CLK_RST_R(reg));
-
-       /* Reset module */
-       writel(we, priv->base + CLK_RST_R(reg));
-
-       /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
-       udelay(35);
-
-       /* Release module from reset state */
-       writel(we | dis, priv->base + CLK_RST_R(reg));
-
-       return 0;
-}
-
 static int rzg2l_cpg_assert(struct reset_controller_dev *rcdev,
                            unsigned long id)
 {
@@ -1158,6 +1135,21 @@ static int rzg2l_cpg_deassert(struct reset_controller_dev *rcdev,
        return 0;
 }
 
+static int rzg2l_cpg_reset(struct reset_controller_dev *rcdev,
+                          unsigned long id)
+{
+       int ret;
+
+       ret = rzg2l_cpg_assert(rcdev, id);
+       if (ret)
+               return ret;
+
+       /* Wait for at least one cycle of the RCLK clock (@ ca. 32 kHz) */
+       udelay(35);
+
+       return rzg2l_cpg_deassert(rcdev, id);
+}
+
 static int rzg2l_cpg_status(struct reset_controller_dev *rcdev,
                            unsigned long id)
 {