asahi: Add XML for unknown 0x4a packet

Enough bits of this packet are known that open-coding hex bytes for it
is annoying. Add some XML correpsonding to what we know.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14219>

diff --git a/src/asahi/lib/cmdbuf.xml b/src/asahi/lib/cmdbuf.xml
index f975eae..2925ee2 100644 (file)
--- a/src/asahi/lib/cmdbuf.xml
+++ b/src/asahi/lib/cmdbuf.xml
@@ -302,6 +302,23 @@
     <field name="Back" size="64" start="4:0" type="Rasterizer face"/>
   </struct>
 
+  <struct name="Unknown face" size="4">
+    <field name="Unknown" size="8" start="0:20" type="hex" default="0x7e"/>
+    <field name="Lines" size="1" start="0:28" type="bool"/>
+    <field name="Points" size="1" start="0:30" type="bool"/>
+  </struct>
+
+  <struct name="Unknown 4a" size="20">
+    <field name="Tag" size="32" start="0:0" type="hex" default="0x200004a"/>
+    <field name="Unk 1" size="1" start="1:9" type="bool" default="true"/>
+    <field name="Lines or points" size="1" start="1:26" type="bool"/>
+    <field name="Reads tilebuffer" size="1" start="1:29" type="bool"/>
+    <field name="Front" size="32" start="2:0" type="Unknown face"/>
+    <field name="Back" size="32" start="3:0" type="Unknown face"/>
+    <!-- maybe sample mask -->
+    <field name="Unk 4" size="32" start="4:0" type="hex" default="0x1ffff"/>
+  </struct>
+
   <struct name="Cull" size="8">
     <field name="Tag" size="32" start="0:0" type="hex" default="0x200000"/>
     <field name="Cull front" size="1" start="1:0" type="bool"/>

diff --git a/src/gallium/drivers/asahi/agx_state.c b/src/gallium/drivers/asahi/agx_state.c
index 3180db8..346e5f7 100644 (file)
--- a/src/gallium/drivers/asahi/agx_state.c
+++ b/src/gallium/drivers/asahi/agx_state.c
@@ -1382,24 +1382,17 @@ demo_rasterizer(struct agx_context *ctx, struct agx_pool *pool, bool is_points)
 static uint64_t
 demo_unk11(struct agx_pool *pool, bool prim_lines, bool prim_points, bool reads_tib)
 {
-#define UNK11_FILL_MODE_LINES_1 (1 << 26)
+   struct agx_ptr T = agx_pool_alloc_aligned(pool, AGX_UNKNOWN_4A_LENGTH, 64);
 
-#define UNK11_FILL_MODE_LINES_2 (0x5004 << 16)
-#define UNK11_LINES (0x10000000)
-#define UNK11_POINTS (0x40000000)
+   agx_pack(T.cpu, UNKNOWN_4A, cfg) {
+      cfg.lines_or_points = (prim_lines || prim_points);
+      cfg.reads_tilebuffer = reads_tib;
 
-#define UNK11_READS_TIB (0x20000000)
-
-   uint32_t unk[] = {
-      0x200004a,
-      0x200 | ((prim_lines || prim_points) ? UNK11_FILL_MODE_LINES_1 : 0) | (reads_tib ? UNK11_READS_TIB : 0),
-      0x7e00000 | (prim_lines ? UNK11_LINES : 0) | (prim_points ? UNK11_POINTS : 0),
-      0x7e00000 | (prim_lines ? UNK11_LINES : 0) | (prim_points ? UNK11_POINTS : 0),
-
-      0x1ffff
+      cfg.front.lines = cfg.back.lines = prim_lines;
+      cfg.front.points = cfg.back.points = prim_points;
    };
 
-   return agx_pool_upload(pool, unk, sizeof(unk));
+   return T.gpu;
 }
 
 static uint64_t