}
#ifdef CONFIG_LCD
+
+void fimd_clk_set()
+{
+ struct s5pc110_clock *clk =
+ (struct s5pc110_clock *)samsung_get_base_clock();
+ unsigned int cfg = 0;
+
+ /* set lcd src clock */
+ cfg = readl(&clk->src1);
+ cfg &= ~(0xf << 20);
+ cfg |= (0x6 << 20);
+ writel(cfg, &clk->src1);
+
+ /* set fimd ratio */
+ cfg = readl(&clk->div1);
+ cfg &= ~(0xf << 20);
+ cfg |= (0x2 << 20);
+ writel(cfg, &clk->div1);
+}
+
#include "../../../drivers/video/s5p-spi.h"
extern void s6e63m0_set_platform_data(struct spi_platform_data *pd);
void fimd_clk_set()
{
+ struct s5pc210_clock *clk =
+ (struct s5pc210_clock *)samsung_get_base_clock();
+
/* workaround */
- unsigned long clk_gate_lcd = 0x1003c934;
- unsigned long mpll_sel_addr = 0x10044200;
- unsigned long clk_mux_addr = 0x10044400;
- unsigned long clk_src_lcd = 0x1003c234;
- unsigned long clk_div_lcd = 0x1003c534;
unsigned long display_ctrl = 0x10010210;
unsigned int cfg = 0;
+ /* LCD0_BLK FIFO S/W reset */
cfg = readl(display_ctrl);
cfg |= (1 << 9);
writel(cfg, display_ctrl);
cfg = 0;
+ /* FIMD of LBLK0 Bypass Selection */
cfg = readl(display_ctrl);
cfg &= ~(1 << 9);
cfg |= (1 << 1);
writel(cfg, display_ctrl);
- cfg = 0;
- cfg = readl(mpll_sel_addr);
- cfg |= (1 << 8);
- writel(cfg, mpll_sel_addr);
-
- cfg = 0;
- cfg = readl(clk_mux_addr);
- cfg |= (0x2 << 8);
- writel(cfg, clk_mux_addr);
-
- cfg = 0;
- cfg = readl(clk_src_lcd);
- cfg |= (0x6 << 0);
- writel(cfg, clk_src_lcd);
-
- cfg = 0;
- cfg = readl(clk_div_lcd);
- cfg |= (0x3 << 0);
- writel(cfg, clk_div_lcd);
-
- cfg = 0;
- cfg = readl(clk_gate_lcd);
- cfg |= (1 << 0);
- writel(cfg, clk_gate_lcd);
+ /* set lcd src clock */
+ cfg = readl(&clk->src_lcd0);
+ cfg &= ~(0xf);
+ cfg |= 0x6;
+ writel(cfg, &clk->src_lcd0);
+
+ /* set fimd ratio */
+ cfg = readl(&clk->div_lcd0);
+ cfg &= ~(0xf);
+ cfg |= 0x2;
+ writel(cfg, &clk->div_lcd0);
}
#include "../../../drivers/video/s5p-spi.h"
COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
COBJS-$(CONFIG_S5PC1XXFB) += s5p-fb.o s5p-fimd.o s5p-spi.o
-COBJS-$(CONFIG_S5PC210FB) += s5pc210-fb.o s5pc210-fimd.o s5p-spi.o
COBJS-$(CONFIG_S6E63M0) += s6e63m0.o
COBJS-$(CONFIG_S6D16A0X) += s6d16a0x.o
COBJS-$(CONFIG_AMS701KA) += ams701ka.o
/* extern void init_onenand_ext2(void); */
extern void init_panel_info(vidinfo_t *vid);
extern int s5p_no_lcd_support(void);
+extern int fimd_clk_set(void);
void lcd_ctrl_init(void *lcdbase)
{
if (s5p_no_lcd_support())
return;
+ fimd_clk_set();
+
s5pc_lcd_init_mem(lcdbase, &panel_info);
/* initialize parameters which is specific to panel. */
#include <asm/arch/gpio.h>
#include "s5p-fb.h"
-/* LCD CONTROLLER REGISTER BASE */
-#define S5PC100_LCRB 0xEE000000
-#define S5PC110_LCRB 0xF8000000
-
#define MPLL 1
static unsigned int ctrl_base;
{
unsigned int cfg = 0, div = 0, fimd_ratio = 0, temp = 0,
remainder, remainder_div;
- unsigned long pixel_clock, src_clock, max_clock;
- struct s5pc110_clock *clk =
- (struct s5pc110_clock *)samsung_get_base_clock();
- u64 div64;
+ unsigned long pixel_clock, src_clock, max_clock, div64;
max_clock = 86 * 1000000;
if (pixel_clock > max_clock)
pixel_clock = max_clock;
- /* set source clock to SCLKMPLL. */
- temp = readl(&clk->src1);
- writel((temp & ~0xf00000) | 0x600000, &clk->src1);
- temp = 0;
-
- /* set fimd ratio to 3. */
- temp = readl(&clk->div1);
- writel((temp & ~0xf00000) | 0x200000, &clk->div1);
- temp = 0;
-
- /* get mpll ratio */
- temp = readl(&clk->div1);
- fimd_ratio = (temp & 0xf00000) >> 20;
- temp = 0;
-
- div64 = ((u64)src_clock) / (fimd_ratio + 1);
+ div64 = get_lcd_clk();
/* get quotient and remainder. */
remainder = do_div(div64, pixel_clock);
pvid = vid;
/* select register base according to cpu type */
- if (cpu_is_s5pc110())
- ctrl_base = S5PC110_LCRB;
- else
- ctrl_base = S5PC100_LCRB;
+ ctrl_base = samsung_get_base_fimd();
/* set output to RGB */
rgb_mode = MODE_RGB_P;
#if 1 /* For LCD test */
#define CONFIG_LCD 1
#define CONFIG_FB_RESERVED_MEM 0x42504000
-#define CONFIG_S5PC210FB 1
+#define CONFIG_S5PC1XXFB 1
#define CONFIG_S6E63M0 1
#define CONFIG_S6D16A0X 1
#define CONFIG_LD9040 1