PD#156734: emmc: refixed core phase value for emmc highspeed busmode

Change-Id: I33ce650b3ed9dd6eac41b0814679fb660991a738
Signed-off-by: Long Yu <long.yu@amlogic.com>

diff --git a/drivers/amlogic/mmc/aml_sd_emmc_v3.c b/drivers/amlogic/mmc/aml_sd_emmc_v3.c
index c7857b8..7ddae86 100644 (file)
--- a/drivers/amlogic/mmc/aml_sd_emmc_v3.c
+++ b/drivers/amlogic/mmc/aml_sd_emmc_v3.c
@@ -241,10 +241,12 @@ static void aml_sd_emmc_set_timing_v3(struct amlsd_host *host,
                        clkc->core_phase  = 2;
                pr_info("%s: try set sd/emmc to DDR mode\n",
                        mmc_hostname(host->mmc));
-       } else if ((timing == MMC_TIMING_MMC_HS)
-               && (host->data->chip_type < MMC_CHIP_G12A))
-               clkc->core_phase = 3;
-       else if ((timing == MMC_TIMING_MMC_HS200)
+       } else if (timing == MMC_TIMING_MMC_HS) {
+               if (host->data->chip_type < MMC_CHIP_G12A)
+                       clkc->core_phase = 3;
+               else
+                       clkc->core_phase = 2;
+       } else if ((timing == MMC_TIMING_MMC_HS200)
                        || ((timing == MMC_TIMING_SD_HS)
                                && aml_card_type_non_sdio(pdata))
                        || (timing == MMC_TIMING_UHS_SDR104)) {