arm64: dts: imx8mq: Add nodes for PCIe IP blocks

Add nodes for two PCIe controllers found on i.MX8MQ.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 253d6d6..2e8c40d 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -6,6 +6,7 @@
 
 #include <dt-bindings/clock/imx8mq-clock.h>
 #include <dt-bindings/power/imx8mq-power.h>
+#include <dt-bindings/reset/imx8mq-reset.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/thermal/thermal.h>
@@ -878,6 +879,66 @@
                        status = "disabled";
                };
 
+
+               pcie0: pcie@33800000 {
+                       compatible = "fsl,imx8mq-pcie";
+                       reg = <0x33800000 0x400000>,
+                             <0x1ff00000 0x80000>;
+                       reg-names = "dbi", "config";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       bus-range = <0x00 0xff>;
+                       ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
+                                 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+                       num-lanes = <1>;
+                       num-viewport = <4>;
+                       interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi";
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+                       fsl,max-link-speed = <2>;
+                       power-domains = <&pgc_pcie>;
+                       resets = <&src IMX8MQ_RESET_PCIEPHY>,
+                                <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+                                <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+                       reset-names = "pciephy", "apps", "turnoff";
+                       status = "disabled";
+               };
+
+               pcie1: pcie@33c00000 {
+                       compatible = "fsl,imx8mq-pcie";
+                       reg = <0x33c00000 0x400000>,
+                             <0x27f00000 0x80000>;
+                       reg-names = "dbi", "config";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       ranges =  <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
+                                  0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
+                       num-lanes = <1>;
+                       num-viewport = <4>;
+                       interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi";
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                       fsl,max-link-speed = <2>;
+                       power-domains = <&pgc_pcie>;
+                       resets = <&src IMX8MQ_RESET_PCIEPHY2>,
+                                <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
+                                <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
+                       reset-names = "pciephy", "apps", "turnoff";
+                       status = "disabled";
+               };
+
                gic: interrupt-controller@38800000 {
                        compatible = "arm,gic-v3";
                        reg = <0x38800000 0x10000>,     /* GIC Dist */