iMX28: Add support for DENX M28EVK board
authorMarek Vasut <marek.vasut@gmail.com>
Tue, 8 Nov 2011 23:18:20 +0000 (23:18 +0000)
committerStefano Babic <sbabic@denx.de>
Fri, 11 Nov 2011 10:36:57 +0000 (11:36 +0100)
This contains support for the following components:
- DUART
- MMC
- Both FEC interfaces
- NAND
- I2C (RTC, EEPROM)
- SPI (FLASH)

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
MAINTAINERS
board/denx/m28evk/Makefile [new file with mode: 0644]
board/denx/m28evk/m28evk.c [new file with mode: 0644]
boards.cfg
include/configs/m28evk.h [new file with mode: 0644]

index 6b5ca89..db1610b 100644 (file)
@@ -859,6 +859,7 @@ Marek Vasut <marek.vasut@gmail.com>
        palmtc          xscale/pxa
        vpac270         xscale/pxa
        zipitz2         xscale/pxa
+       m28evk          i.MX28
        efikamx         i.MX51
        efikasb         i.MX51
 
diff --git a/board/denx/m28evk/Makefile b/board/denx/m28evk/Makefile
new file mode 100644 (file)
index 0000000..e6aba9a
--- /dev/null
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = $(obj)lib$(BOARD).o
+
+COBJS  := m28evk.o
+
+SRCS   := $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+
+$(LIB):        $(obj).depend $(OBJS)
+       $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/denx/m28evk/m28evk.c b/board/denx/m28evk/m28evk.c
new file mode 100644 (file)
index 0000000..118e222
--- /dev/null
@@ -0,0 +1,195 @@
+/*
+ * DENX M28 module
+ *
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Functions
+ */
+int board_early_init_f(void)
+{
+       /* IO0 clock at 480MHz */
+       mx28_set_ioclk(MXC_IOCLK0, 480000);
+       /* IO1 clock at 480MHz */
+       mx28_set_ioclk(MXC_IOCLK1, 480000);
+
+       /* SSP0 clock at 96MHz */
+       mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
+       /* SSP2 clock at 96MHz */
+       mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
+
+       return 0;
+}
+
+int board_init(void)
+{
+       /* Adress of boot parameters */
+       gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+       return 0;
+}
+
+int dram_init(void)
+{
+       /* dram_init must store complete ramsize in gd->ram_size */
+       gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
+       return 0;
+}
+
+#ifdef CONFIG_CMD_MMC
+static int m28_mmc_wp(int id)
+{
+       if (id != 0) {
+               printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
+               return 1;
+       }
+
+       return gpio_get_value(MX28_PAD_AUART2_CTS__GPIO_3_10);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+       /* Configure WP as output */
+       gpio_direction_input(MX28_PAD_AUART2_CTS__GPIO_3_10);
+
+       return mxsmmc_initialize(bis, 0, m28_mmc_wp);
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+
+#define        MII_OPMODE_STRAP_OVERRIDE       0x16
+#define        MII_PHY_CTRL1                   0x1e
+#define        MII_PHY_CTRL2                   0x1f
+
+int fecmxc_mii_postcall(int phy)
+{
+       miiphy_write("FEC1", phy, MII_BMCR, 0x9000);
+       miiphy_write("FEC1", phy, MII_OPMODE_STRAP_OVERRIDE, 0x0202);
+       if (phy == 3)
+               miiphy_write("FEC1", 3, MII_PHY_CTRL2, 0x8180);
+       return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+       struct mx28_clkctrl_regs *clkctrl_regs =
+               (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+       struct eth_device *dev;
+       int ret;
+
+       ret = cpu_eth_init(bis);
+
+       clrsetbits_le32(&clkctrl_regs->hw_clkctrl_enet,
+               CLKCTRL_ENET_TIME_SEL_MASK | CLKCTRL_ENET_CLK_OUT_EN,
+               CLKCTRL_ENET_TIME_SEL_RMII_CLK);
+
+       ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
+       if (ret) {
+               printf("FEC MXS: Unable to init FEC0\n");
+               return ret;
+       }
+
+       ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
+       if (ret) {
+               printf("FEC MXS: Unable to init FEC1\n");
+               return ret;
+       }
+
+       dev = eth_get_dev_by_name("FEC0");
+       if (!dev) {
+               printf("FEC MXS: Unable to get FEC0 device entry\n");
+               return -EINVAL;
+       }
+
+       ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+       if (ret) {
+               printf("FEC MXS: Unable to register FEC0 mii postcall\n");
+               return ret;
+       }
+
+       dev = eth_get_dev_by_name("FEC1");
+       if (!dev) {
+               printf("FEC MXS: Unable to get FEC1 device entry\n");
+               return -EINVAL;
+       }
+
+       ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+       if (ret) {
+               printf("FEC MXS: Unable to register FEC1 mii postcall\n");
+               return ret;
+       }
+
+       return ret;
+}
+
+#ifdef CONFIG_M28_FEC_MAC_IN_OCOTP
+
+#define        MXS_OCOTP_MAX_TIMEOUT   1000000
+void imx_get_mac_from_fuse(char *mac)
+{
+       struct mx28_ocotp_regs *ocotp_regs =
+               (struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
+       uint32_t data;
+
+       memset(mac, 0, 6);
+
+       writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
+
+       if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
+                               MXS_OCOTP_MAX_TIMEOUT)) {
+               printf("MXS FEC: Can't get MAC from OCOTP\n");
+               return;
+       }
+
+       data = readl(&ocotp_regs->hw_ocotp_cust0);
+
+       mac[0] = 0x00;
+       mac[1] = 0x04;
+       mac[2] = (data >> 24) & 0xff;
+       mac[3] = (data >> 16) & 0xff;
+       mac[4] = (data >> 8) & 0xff;
+       mac[5] = data & 0xff;
+}
+#else
+void imx_get_mac_from_fuse(char *mac)
+{
+       memset(mac, 0, 6);
+}
+#endif
+
+#endif
index cf6e67c..bbf589e 100644 (file)
@@ -158,6 +158,7 @@ tx25                         arm         arm926ejs   tx25                karo
 zmx25                        arm         arm926ejs   zmx25               syteco         mx25
 imx27lite                    arm         arm926ejs   imx27lite           logicpd        mx27
 magnesium                    arm         arm926ejs   imx27lite           logicpd        mx27
+m28evk                       arm         arm926ejs   -                   denx           mx28
 nhk8815                      arm         arm926ejs   nhk8815             st             nomadik
 nhk8815_onenand              arm         arm926ejs   nhk8815             st             nomadik       nhk8815:BOOT_ONENAND
 omap5912osk                  arm         arm926ejs   -                   ti             omap
diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
new file mode 100644 (file)
index 0000000..d88e09e
--- /dev/null
@@ -0,0 +1,282 @@
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ * on behalf of DENX Software Engineering GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __M28_H__
+#define __M28_H__
+
+#include <asm/arch/regs-base.h>
+
+/*
+ * SoC configurations
+ */
+#define        CONFIG_MX28                             /* i.MX28 SoC */
+#define        CONFIG_MXS_GPIO                         /* GPIO control */
+#define        CONFIG_SYS_HZ           1000            /* Ticks per second */
+
+/*
+ * Define M28EVK machine type by hand until it lands in mach-types
+ */
+#define        MACH_TYPE_M28EVK        3613
+
+#define        CONFIG_MACH_TYPE        MACH_TYPE_M28EVK
+
+#define        CONFIG_SYS_NO_FLASH
+#define        CONFIG_SYS_ICACHE_OFF
+#define        CONFIG_SYS_DCACHE_OFF
+#define        CONFIG_BOARD_EARLY_INIT_F
+#define        CONFIG_ARCH_CPU_INIT
+
+/*
+ * U-Boot Commands
+ */
+#include <config_cmd_default.h>
+#define        CONFIG_DISPLAY_CPUINFO
+#define        CONFIG_DOS_PARTITION
+
+#define        CONFIG_CMD_CACHE
+#define        CONFIG_CMD_DATE
+#define        CONFIG_CMD_DHCP
+#define        CONFIG_CMD_EEPROM
+#define        CONFIG_CMD_EXT2
+#define        CONFIG_CMD_FAT
+#define        CONFIG_CMD_GPIO
+#define        CONFIG_CMD_I2C
+#define        CONFIG_CMD_MII
+#define        CONFIG_CMD_MMC
+#define        CONFIG_CMD_NAND
+#define        CONFIG_CMD_NET
+#define        CONFIG_CMD_NFS
+#define        CONFIG_CMD_PING
+#define        CONFIG_CMD_SETEXPR
+#define        CONFIG_CMD_SF
+#define        CONFIG_CMD_SPI
+
+/*
+ * Memory configurations
+ */
+#define        CONFIG_NR_DRAM_BANKS            1               /* 2 banks of DRAM */
+#define        PHYS_SDRAM_1                    0x40000000      /* Base address */
+#define        PHYS_SDRAM_1_SIZE               0x08000000      /* 128 MB */
+#define        CONFIG_STACKSIZE                0x00010000      /* 128 KB stack */
+#define        CONFIG_SYS_MALLOC_LEN           0x00400000      /* 4 MB for malloc */
+#define        CONFIG_SYS_GBL_DATA_SIZE        128             /* Initial data */
+#define        CONFIG_SYS_MEMTEST_START        0x40000000      /* Memtest start adr */
+#define        CONFIG_SYS_MEMTEST_END          0x40400000      /* 4 MB RAM test */
+#define        CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
+/* Point initial SP in SRAM so SPL can use it too. */
+#define        CONFIG_SYS_INIT_SP_ADDR         0x00002000
+/*
+ * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
+ * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
+ * binary. In case there was more of this mess, 0x100 bytes are skipped.
+ */
+#define        CONFIG_SYS_TEXT_BASE            0x40000100
+
+/*
+ * U-Boot general configurations
+ */
+#define        CONFIG_SYS_LONGHELP
+#define        CONFIG_SYS_PROMPT       "=> "
+#define        CONFIG_SYS_CBSIZE       1024            /* Console I/O buffer size */
+#define        CONFIG_SYS_PBSIZE       \
+       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+                                               /* Print buffer size */
+#define        CONFIG_SYS_MAXARGS      32              /* Max number of command args */
+#define        CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
+                                               /* Boot argument buffer size */
+#define        CONFIG_VERSION_VARIABLE                 /* U-BOOT version */
+#define        CONFIG_AUTO_COMPLETE                    /* Command auto complete */
+#define        CONFIG_CMDLINE_EDITING                  /* Command history etc */
+#define        CONFIG_SYS_HUSH_PARSER
+#define        CONFIG_SYS_PROMPT_HUSH_PS2      "> "
+
+/*
+ * Serial Driver
+ */
+#define        CONFIG_PL011_SERIAL
+#define        CONFIG_PL011_CLOCK              24000000
+#define        CONFIG_PL01x_PORTS              { (void *)MXS_UARTDBG_BASE }
+#define        CONFIG_CONS_INDEX               0
+#define        CONFIG_BAUDRATE                 115200  /* Default baud rate */
+#define        CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * MMC Driver
+ */
+#ifdef CONFIG_CMD_MMC
+#define        CONFIG_MMC
+#define        CONFIG_GENERIC_MMC
+#define        CONFIG_MXS_MMC
+#endif
+
+/*
+ * NAND
+ */
+#ifdef CONFIG_CMD_NAND
+#define        CONFIG_NAND_MXS
+#define CONFIG_APBH_DMA
+#define        CONFIG_SYS_MAX_NAND_DEVICE      1
+#define        CONFIG_SYS_NAND_BASE            0x60000000
+#define        CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define        NAND_MAX_CHIPS                  8
+
+/* Environment is in NAND */
+#define        CONFIG_ENV_IS_IN_NAND
+#define        CONFIG_ENV_SIZE                 (16 * 1024)
+#define        CONFIG_ENV_SIZE_REDUND          CONFIG_ENV_SIZE
+#define        CONFIG_ENV_SECT_SIZE            (128 * 1024)
+#define        CONFIG_ENV_RANGE                (512 * 1024)
+#define        CONFIG_ENV_OFFSET               0x300000
+#define        CONFIG_ENV_OFFSET_REDUND        \
+               (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
+
+#define        CONFIG_CMD_UBI
+#define        CONFIG_CMD_UBIFS
+#define        CONFIG_CMD_MTDPARTS
+#define        CONFIG_RBTREE
+#define        CONFIG_LZO
+#define        CONFIG_MTD_DEVICE
+#define        CONFIG_MTD_PARTITIONS
+#define        MTDIDS_DEFAULT                  "nand0=gpmi-nand.0"
+#define        MTDPARTS_DEFAULT                        \
+       "mtdparts=gpmi-nand.0:"                 \
+               "3m(bootloader)ro,"             \
+               "512k(environment),"            \
+               "512k(redundant-environment),"  \
+               "4m(kernel),"                   \
+               "-(filesystem)"
+#endif
+
+/*
+ * Ethernet on SOC (FEC)
+ */
+#ifdef CONFIG_CMD_NET
+#define        CONFIG_NET_MULTI
+#define        CONFIG_ETHPRIME                 "FEC0"
+#define        CONFIG_FEC_MXC
+#define        CONFIG_FEC_MXC_MULTI
+#define        CONFIG_MII
+#define        CONFIG_DISCOVER_PHY
+#define        CONFIG_FEC_XCV_TYPE             RMII
+#endif
+
+/*
+ * I2C
+ */
+#ifdef CONFIG_CMD_I2C
+#define        CONFIG_I2C_MXS
+#define        CONFIG_HARD_I2C
+#define        CONFIG_SYS_I2C_SPEED            400000
+#endif
+
+/*
+ * EEPROM
+ */
+#ifdef CONFIG_CMD_EEPROM
+#define        CONFIG_SYS_I2C_MULTI_EEPROMS
+#define        CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
+#endif
+
+/*
+ * RTC
+ */
+#ifdef CONFIG_CMD_DATE
+/* Use the internal RTC in the MXS chip */
+#define        CONFIG_RTC_INTERNAL
+#ifdef CONFIG_RTC_INTERNAL
+#define        CONFIG_RTC_MXS
+#else
+#define        CONFIG_RTC_M41T62
+#define        CONFIG_SYS_I2C_RTC_ADDR         0x68
+#define        CONFIG_SYS_M41T11_BASE_YEAR     2000
+#endif
+#endif
+
+/*
+ * SPI
+ */
+#ifdef CONFIG_CMD_SPI
+#define        CONFIG_HARD_SPI
+#define        CONFIG_MXS_SPI
+#define        CONFIG_SPI_HALF_DUPLEX
+#define        CONFIG_DEFAULT_SPI_BUS          2
+#define        CONFIG_DEFAULT_SPI_MODE         SPI_MODE_0
+
+/* SPI FLASH */
+#ifdef CONFIG_CMD_SF
+#define        CONFIG_SPI_FLASH
+#define        CONFIG_SPI_FLASH_STMICRO
+#define        CONFIG_SPI_FLASH_CS             2
+#define        CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
+#define        CONFIG_SF_DEFAULT_SPEED         24000000
+
+#define        CONFIG_ENV_SPI_CS               0
+#define        CONFIG_ENV_SPI_BUS              2
+#define        CONFIG_ENV_SPI_MAX_HZ           24000000
+#define        CONFIG_ENV_SPI_MODE             SPI_MODE_0
+#endif
+#endif
+
+/*
+ * Boot Linux
+ */
+#define        CONFIG_CMDLINE_TAG
+#define        CONFIG_SETUP_MEMORY_TAGS
+#define        CONFIG_BOOTDELAY        3
+#define        CONFIG_BOOTFILE         "uImage"
+#define        CONFIG_BOOTARGS         "console=ttyAM0,115200n8 "
+#define        CONFIG_BOOTCOMMAND      "run bootcmd_net"
+#define        CONFIG_LOADADDR         0x42000000
+#define        CONFIG_SYS_LOAD_ADDR    CONFIG_LOADADDR
+
+/*
+ * Extra Environments
+ */
+#define        CONFIG_EXTRA_ENV_SETTINGS                                       \
+       "update_nand_full_filename=u-boot.nand\0"                       \
+       "update_nand_firmware_filename=u-boot.sb\0"                     \
+       "update_nand_firmware_maxsz=0x100000\0"                         \
+       "update_nand_stride=0x40\0"     /* MX28 datasheet ch. 12.12 */  \
+       "update_nand_count=0x4\0"       /* MX28 datasheet ch. 12.12 */  \
+       "update_nand_get_fcb_size="     /* Get size of FCB blocks */    \
+               "nand device 0 ; "                                      \
+               "nand info ; "                                          \
+               "setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \
+               "setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \
+       "update_nand_full="             /* Update FCB, DBBT and FW */   \
+               "if tftp ${update_nand_full_filename} ; then "          \
+               "run update_nand_get_fcb_size ; "                       \
+               "nand scrub -y 0x0 ${filesize} ; "                      \
+               "nand write.raw ${loadaddr} 0x0 ${update_nand_fcb} ; "  \
+               "setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \
+               "setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \
+               "nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \
+               "fi\0"                                                  \
+       "update_nand_firmware="         /* Update only firmware */      \
+               "if tftp ${update_nand_firmware_filename} ; then "      \
+               "run update_nand_get_fcb_size ; "                       \
+               "setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \
+               "setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; "    \
+               "setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \
+               "nand erase ${fcb_sz} ${fw_sz} ; "                      \
+               "nand write ${loadaddr} ${fcb_sz} ${filesize} ; "       \
+               "nand write ${loadaddr} ${fw_off} ${filesize} ; "       \
+               "fi\0"
+
+#endif /* __M28_H__ */