+2014-04-04 Jeff Law <law@redhat.com>
+
+ PR target/60657
+ * config/arm/predicates.md (const_int_I_operand): New predicate.
+ (const_int_M_operand): Similarly.
+ * config/arm/arm.md (insv_zero): Use const_int_M_operand instead of
+ const_int_operand.
+ (insv_t2, extv_reg, extzv_t2): Likewise.
+ (load_multiple_with_writeback): Similarly for const_int_I_operand.
+ (pop_multiple_with_writeback_and_return): Likewise.
+ (vfp_pop_multiple_with_writeback): Likewise
+
2014-04-04 Richard Biener <rguenther@suse.de>
PR ipa/60746
(define_insn "insv_zero"
[(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r")
- (match_operand:SI 1 "const_int_operand" "M")
- (match_operand:SI 2 "const_int_operand" "M"))
+ (match_operand:SI 1 "const_int_M_operand" "M")
+ (match_operand:SI 2 "const_int_M_operand" "M"))
(const_int 0))]
"arm_arch_thumb2"
"bfc%?\t%0, %2, %1"
(define_insn "insv_t2"
[(set (zero_extract:SI (match_operand:SI 0 "s_register_operand" "+r")
- (match_operand:SI 1 "const_int_operand" "M")
- (match_operand:SI 2 "const_int_operand" "M"))
+ (match_operand:SI 1 "const_int_M_operand" "M")
+ (match_operand:SI 2 "const_int_M_operand" "M"))
(match_operand:SI 3 "s_register_operand" "r"))]
"arm_arch_thumb2"
"bfi%?\t%0, %3, %2, %1"
(define_insn "*extv_reg"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(sign_extract:SI (match_operand:SI 1 "s_register_operand" "r")
- (match_operand:SI 2 "const_int_operand" "M")
- (match_operand:SI 3 "const_int_operand" "M")))]
+ (match_operand:SI 2 "const_int_M_operand" "M")
+ (match_operand:SI 3 "const_int_M_operand" "M")))]
"arm_arch_thumb2"
"sbfx%?\t%0, %1, %3, %2"
[(set_attr "length" "4")
(define_insn "extzv_t2"
[(set (match_operand:SI 0 "s_register_operand" "=r")
(zero_extract:SI (match_operand:SI 1 "s_register_operand" "r")
- (match_operand:SI 2 "const_int_operand" "M")
- (match_operand:SI 3 "const_int_operand" "M")))]
+ (match_operand:SI 2 "const_int_M_operand" "M")
+ (match_operand:SI 3 "const_int_M_operand" "M")))]
"arm_arch_thumb2"
"ubfx%?\t%0, %1, %3, %2"
[(set_attr "length" "4")
[(match_parallel 0 "load_multiple_operation"
[(set (match_operand:SI 1 "s_register_operand" "+rk")
(plus:SI (match_dup 1)
- (match_operand:SI 2 "const_int_operand" "I")))
+ (match_operand:SI 2 "const_int_I_operand" "I")))
(set (match_operand:SI 3 "s_register_operand" "=rk")
(mem:SI (match_dup 1)))
])]
[(return)
(set (match_operand:SI 1 "s_register_operand" "+rk")
(plus:SI (match_dup 1)
- (match_operand:SI 2 "const_int_operand" "I")))
+ (match_operand:SI 2 "const_int_I_operand" "I")))
(set (match_operand:SI 3 "s_register_operand" "=rk")
(mem:SI (match_dup 1)))
])]
[(match_parallel 0 "pop_multiple_fp"
[(set (match_operand:SI 1 "s_register_operand" "+rk")
(plus:SI (match_dup 1)
- (match_operand:SI 2 "const_int_operand" "I")))
+ (match_operand:SI 2 "const_int_I_operand" "I")))
(set (match_operand:DF 3 "vfp_hard_register_operand" "")
(mem:DF (match_dup 1)))])]
"TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
(ior (match_operand 0 "arm_rhs_operand")
(match_operand 0 "memory_operand")))
+(define_predicate "const_int_I_operand"
+ (and (match_operand 0 "const_int_operand")
+ (match_test "satisfies_constraint_I (op)")))
+
+(define_predicate "const_int_M_operand"
+ (and (match_operand 0 "const_int_operand")
+ (match_test "satisfies_constraint_M (op)")))
+
;; This doesn't have to do much because the constant is already checked
;; in the shift_operator predicate.
(define_predicate "shift_amount_operand"