cfg->hsc_div_length = (124 << 24) / cfg->hsc_phase_step;
multo = cfg->hsc_phase_step * cfg->hsc_div_length;
-#ifndef CONFIG_GE2D_ADV_NUM
cfg->hsc_adv_num = multo >> 24;
-#endif
cfg->hsc_adv_phase = multo & 0xffffff;
}
);
if (cfg->hsc_adv_num > 255)
cfg->hsc_adv_num = cfg->hsc_adv_num >> 8;
+ else
+ cfg->hsc_adv_num = 0;
ge2d_reg_write(GE2D_HSC_INI_CTRL,
(cfg->hsc_rpt_p0_num << 29) |
(cfg->hsc_adv_num << 24) |
- (cfg->hsc_ini_phase << 0)
+ ((cfg->hsc_ini_phase & 0xffffff) << 0)
);
#else
ge2d_reg_write(GE2D_HSC_ADV_CTRL,
);
ge2d_reg_write(GE2D_HSC_INI_CTRL,
(cfg->hsc_rpt_p0_num << 29) |
- (cfg->hsc_ini_phase << 0)
+ ((cfg->hsc_ini_phase & 0xffffff) << 0)
);
#endif
#define MAX_BITBLT_WORK_CONFIG 4
#define MAX_GE2D_CMD 32 /* 64 */
-/* #define CONFIG_GE2D_ADV_NUM */
+#define CONFIG_GE2D_ADV_NUM
#define CONFIG_GE2D_SRC2
#define GE2D_STATE_IDLE 0
#define GE2D_STATE_RUNNING 1