{
u32 thresh, value, frame_start, mw_ack_done;
int bytes_per_line = chan->format.bytesperline;
+ u32 sizeimage = chan->format.sizeimage;
int err;
/* program buffer address by using surface 0 */
vi_csi_write(chan, TEGRA_VI_CSI_SURFACE0_STRIDE, bytes_per_line);
/*
+ * Program surface 1 for UV plane with offset sizeimage from Y plane.
+ */
+ if (chan->fmtinfo->fourcc == V4L2_PIX_FMT_NV16) {
+ vi_csi_write(chan, TEGRA_VI_CSI_SURFACE1_OFFSET_MSB,
+ ((u64)buf->addr + sizeimage / 2) >> 32);
+ vi_csi_write(chan, TEGRA_VI_CSI_SURFACE1_OFFSET_LSB,
+ buf->addr + sizeimage / 2);
+ vi_csi_write(chan, TEGRA_VI_CSI_SURFACE1_STRIDE,
+ bytes_per_line);
+ }
+
+ /*
* Tegra VI block interacts with host1x syncpt for synchronizing
* programmed condition of capture state and hardware operation.
* Frame start and Memory write acknowledge syncpts has their own
pix->bytesperline = clamp(bpl, min_bpl, max_bpl);
pix->sizeimage = pix->bytesperline * pix->height;
+ if (pix->pixelformat == V4L2_PIX_FMT_NV16)
+ pix->sizeimage *= 2;
}
static int __tegra_channel_try_format(struct tegra_vi_channel *chan,