title: PCIe RC controller on Intel Gateway SoCs
maintainers:
- - Dilip Kota <eswara.kota@linux.intel.com>
+ - Rahul Tanwar <rtanwar@maxlinear.com>
select:
properties:
required:
- compatible
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie.yaml#
+
properties:
compatible:
items:
- const: intel,lgm-pcie
- const: snps,dw-pcie
- device_type:
- const: pci
-
- "#address-cells":
- const: 3
-
- "#size-cells":
- const: 2
-
reg:
items:
- description: Controller control and status registers.
reset-gpios:
maxItems: 1
- linux,pci-domain: true
-
num-lanes:
maximum: 2
- description: Number of lanes to use for this port.
-
- '#interrupt-cells':
- const: 1
-
- interrupt-map-mask:
- description: Standard PCI IRQ mapping properties.
-
- interrupt-map:
- description: Standard PCI IRQ mapping properties.
max-link-speed:
- description: Specify PCI Gen for link capability.
- $ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 3, 4]
default: 1
- bus-range:
- description: Range of bus numbers associated with this controller.
-
reset-assert-ms:
description: |
Delay after asserting reset to the PCIe device.
required:
- compatible
- - device_type
- - "#address-cells"
- - "#size-cells"
- reg
- reg-names
- ranges
- interrupt-map
- interrupt-map-mask
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |