dm: pcie_fsl: Fix the calculation of controller index

The PCIe controller register address in CCSR is different
on various platforms, the current code erroneously use
the hardcoded address (0xffe240000) and stride (0x10000)
to calculate the controller's index.

Fix it by adding the related info to the driver data
structure.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 1be5063..d3d2c19 100644 (file)
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -582,6 +582,7 @@ static int fsl_pcie_probe(struct udevice *dev)
 static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)
 {
        struct fsl_pcie *pcie = dev_get_priv(dev);
+       struct fsl_pcie_data *info;
        int ret;
 
        pcie->regs = dev_remap_addr(dev);
@@ -596,7 +597,10 @@ static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)
                return ret;
        }
 
-       pcie->idx = (dev_read_addr(dev) - 0xffe240000) / 0x10000;
+       info = (struct fsl_pcie_data *)dev_get_driver_data(dev);
+       pcie->info = info;
+       pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) -
+                   info->block_offset) / info->stride;
 
        return 0;
 }
@@ -606,8 +610,14 @@ static const struct dm_pci_ops fsl_pcie_ops = {
        .write_config   = fsl_pcie_write_config,
 };
 
+static struct fsl_pcie_data t2080_data = {
+       .block_offset = 0x240000,
+       .block_offset_mask = 0x3fffff,
+       .stride = 0x10000,
+};
+
 static const struct udevice_id fsl_pcie_ids[] = {
-       { .compatible = "fsl,pcie-t2080" },
+       { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
        { }
 };
 

diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h
index 032775c..dc8368d 100644 (file)
--- a/drivers/pci/pcie_fsl.h
+++ b/drivers/pci/pcie_fsl.h
@@ -43,6 +43,12 @@
 #define LTSSM_L0_REV3                  0x11
 #define LTSSM_L0                       0x16
 
+struct fsl_pcie_data {
+       u32 block_offset;               /* Offset from CCSR of 1st controller */
+       u32 block_offset_mask;          /* Mask out the CCSR base */
+       u32 stride;                     /* Offset stride between controllers */
+};
+
 struct fsl_pcie {
        int idx;
        struct udevice *bus;
@@ -52,6 +58,7 @@ struct fsl_pcie {
        bool mode;                      /* RC&EP mode flag */
        bool enabled;                   /* Enable status */
        struct list_head list;
+       struct fsl_pcie_data *info;
 };
 
 extern struct list_head fsl_pcie_list;