[ARM] Fix the type for v4f16 duplane

This was previously using the 32bit variant of the instruction, instead
of the 16bit as intended.

Fixes #58512

Differential Revision: https://reviews.llvm.org/D136422

diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td
index 79d3cf7..6b7a4a4 100644 (file)
--- a/llvm/lib/Target/ARM/ARMInstrNEON.td
+++ b/llvm/lib/Target/ARM/ARMInstrNEON.td
@@ -6697,7 +6697,7 @@ def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
 
 let Predicates = [HasNEON] in {
 def : Pat<(v4f16 (ARMvduplane (v4f16 DPR:$Vm), imm:$lane)),
-          (VDUPLN32d DPR:$Vm, imm:$lane)>;
+          (VDUPLN16d DPR:$Vm, imm:$lane)>;
 
 def : Pat<(v2f32 (ARMvduplane (v2f32 DPR:$Vm), imm:$lane)),
           (VDUPLN32d DPR:$Vm, imm:$lane)>;

diff --git a/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll b/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
index 37e3488..24d9c88 100644 (file)
--- a/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
+++ b/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
@@ -1379,7 +1379,7 @@ entry:
 define dso_local <4 x half> @test_vdup_lane_f16(<4 x half> %a) {
 ; CHECK-LABEL: test_vdup_lane_f16:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vdup.32 d0, d0[3]
+; CHECK-NEXT:    vdup.16 d0, d0[3]
 ; CHECK-NEXT:    bx lr
 entry:
   %shuffle = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>