[NFCI] Fixed missing colon in CHECK directives - part 2

diff --git a/llvm/test/Analysis/ScalarEvolution/trivial-phis.ll b/llvm/test/Analysis/ScalarEvolution/trivial-phis.ll
index 2128448..b3192cb 100644 (file)
--- a/llvm/test/Analysis/ScalarEvolution/trivial-phis.ll
+++ b/llvm/test/Analysis/ScalarEvolution/trivial-phis.ll
@@ -1,6 +1,6 @@
 ; RUN: opt -passes='print<scalar-evolution>' -disable-output %s 2>&1 | FileCheck %s
 
-; CHECK-LABEL @test1
+; CHECK-LABEL: @test1
 ; CHECK:       %add.lcssa.wide = phi i64 [ %indvars.iv.next, %do.body ]
 ; CHECK-NEXT:  -->  %add.lcssa.wide U: [1,2147483648) S: [1,2147483648)
 
@@ -22,7 +22,7 @@ do.end:                                           ; preds = %do.body
   ret i64 %add.lcssa.wide
 }
 
-; CHECK-LABEL @test2
+; CHECK-LABEL: @test2
 ; CHECK:      %tmp24 = phi i64 [ %tmp14, %bb22 ], [ %tmp14, %bb13 ]
 ; CHECK-NEXT: -->  %tmp24 U: full-set S: full-set       Exits: <<Unknown>>      LoopDispositions: { %bb13: Variant, %bb8: Variant, %bb17: Invariant, %bb27: Invariant }
 
@@ -114,7 +114,7 @@ bb48:                                             ; preds = %bb47, %bb
   ret void
 }
 
-; CHECK-LABEL @test3
+; CHECK-LABEL: @test3
 
 ; CHECK:      %tmp14 = phi i64 [ %tmp40, %bb39 ], [ 1, %bb8 ]
 ; CHECK-NEXT: -->  {1,+,1}<%bb13> U: [1,9223372036854775807) S: [1,9223372036854775807)

diff --git a/llvm/test/CodeGen/AArch64/arm64-inline-asm.ll b/llvm/test/CodeGen/AArch64/arm64-inline-asm.ll
index 86e2d2e..5bfc324 100644 (file)
--- a/llvm/test/CodeGen/AArch64/arm64-inline-asm.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-inline-asm.ll
@@ -494,7 +494,6 @@ define void @test_vector_too_large_r_m(<9 x float>* nocapture readonly %0) {
 ; CHECK-NEXT:    ; InlineAsm End
 ; CHECK-NEXT:    add sp, sp, #64
 ; CHECK-NEXT:    ret
-; CHECK-DAG   stp [[Q0]], [[Q1]], [sp]
 entry:
   %m.addr = alloca <9 x float>, align 16
   %m = load <9 x float>, <9 x float>* %0, align 16

diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-vselect.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-vselect.ll
index 9d89649..2380a4c 100644 (file)
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-vselect.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-vselect.ll
@@ -181,13 +181,13 @@ define void @select_v16f32(<16 x float>* %a, <16 x float>* %b) #0 {
 define void @select_v32f32(<32 x float>* %a, <32 x float>* %b) #0 {
 ; VBITS_GE_1024-LABEL: select_v32f32:
 ; VBITS_GE_1024:       // %bb.0:
-; VBITS_GE_1024-NEXT     ptrue   p0.s, vl32
-; VBITS_GE_1024-NEXT     ld1w    { z0.s }, p0/z, [x0]
-; VBITS_GE_1024-NEXT     ld1w    { z1.s }, p0/z, [x1]
-; VBITS_GE_1024-NEXT     fcmeq   p1.s, p0/z, z0.s, z1.s
-; VBITS_GE_1024-NEXT     sel     z0.s, p1, z0.s, z1.s
-; VBITS_GE_1024-NEXT     st1w    { z0.s }, p0, [x0]
-; VBITS_GE_1024-NEXT     ret
+; VBITS_GE_1024-NEXT:     ptrue   p0.s, vl32
+; VBITS_GE_1024-NEXT:     ld1w    { z0.s }, p0/z, [x0]
+; VBITS_GE_1024-NEXT:     ld1w    { z1.s }, p0/z, [x1]
+; VBITS_GE_1024-NEXT:     fcmeq   p1.s, p0/z, z0.s, z1.s
+; VBITS_GE_1024-NEXT:     sel     z0.s, p1, z0.s, z1.s
+; VBITS_GE_1024-NEXT:     st1w    { z0.s }, p0, [x0]
+; VBITS_GE_1024-NEXT:     ret
   %op1 = load <32 x float>, <32 x float>* %a
   %op2 = load <32 x float>, <32 x float>* %b
   %mask = fcmp oeq <32 x float> %op1, %op2

diff --git a/llvm/test/CodeGen/ARM/two-part-imm.ll b/llvm/test/CodeGen/ARM/two-part-imm.ll
index ccbe817..c04aca3 100644 (file)
--- a/llvm/test/CodeGen/ARM/two-part-imm.ll
+++ b/llvm/test/CodeGen/ARM/two-part-imm.ll
@@ -8,13 +8,13 @@
 define i32 @sub0(i32 %0) {
 ; CHECK-ARM-LABEL: sub0:
 ; CHECK-ARM:       @ %bb.0:
-; CHECK-ARM:         sub r0, r0, #23
-; CHECK-ARM:         mov pc, lr
+; CHECK-ARM-NEXT:    sub r0, r0, #23
+; CHECK-ARM-NEXT:    mov pc, lr
 ;
 ; CHECK-THUMB2-LABEL: sub0:
 ; CHECK-THUMB2:       @ %bb.0:
-; CHECK-THUMB2:         subs r0, #23
-; CHECK-THUMB2:         bx lr
+; CHECK-THUMB2-NEXT:    subs r0, #23
+; CHECK-THUMB2-NEXT:    bx lr
   %2 = sub i32 %0, 23
   ret i32 %2
 }
@@ -22,20 +22,20 @@ define i32 @sub0(i32 %0) {
 define i32 @sub1(i32 %0) {
 ; CHECK-ARM-LABEL: sub1:
 ; CHECK-ARM:       @ %bb.0:
-; CHECK-ARM:         ldr r1, .LCPI1_0
-; CHECK-ARM:         add r0, r0, r1
-; CHECK-ARM:         mov pc, lr
-; CHECK-ARM:         .p2align 2
-; CHECK-ARM:       @ %bb.1:
-; CHECK-ARM:         .LCPI1_0:
-; CHECK-ARM:         .long 4294836225 @ 0xfffe0001
+; CHECK-ARM-NEXT:    ldr r1, .LCPI1_0
+; CHECK-ARM-NEXT:    add r0, r0, r1
+; CHECK-ARM-NEXT:    mov pc, lr
+; CHECK-ARM-NEXT:    .p2align 2
+; CHECK-ARM-NEXT:  @ %bb.1:
+; CHECK-ARM-NEXT:  .LCPI1_0:
+; CHECK-ARM-NEXT:    .long 4294836225 @ 0xfffe0001
 ;
 ; CHECK-THUMB2-LABEL: sub1:
 ; CHECK-THUMB2:       @ %bb.0:
-; CHECK-THUMB2          movs r1, #1
-; CHECK-THUMB2          movt r1, #65534
-; CHECK-THUMB2          add r0, r1
-; CHECK-THUMB2          bx lr
+; CHECK-THUMB2-NEXT:    movs r1, #1
+; CHECK-THUMB2-NEXT:    movt r1, #65534
+; CHECK-THUMB2-NEXT:    add r0, r1
+; CHECK-THUMB2-NEXT:    bx lr
   %2 = sub i32 %0, 131071
   ret i32 %2
 }
@@ -43,15 +43,15 @@ define i32 @sub1(i32 %0) {
 define i32 @sub2(i32 %0) {
 ; CHECK-ARM-LABEL: sub2:
 ; CHECK-ARM:       @ %bb.0:
-; CHECK-ARM:         sub r0, r0, #35
-; CHECK-ARM:         sub r0, r0, #8960
-; CHECK-ARM:         mov pc, lr
+; CHECK-ARM-NEXT:    sub r0, r0, #35
+; CHECK-ARM-NEXT:    sub r0, r0, #8960
+; CHECK-ARM-NEXT:    mov pc, lr
 ;
 ; CHECK-THUMB2-LABEL: sub2:
 ; CHECK-THUMB2:       @ %bb.0:
-; CHECK-THUMB2:         movw r1, #8995
-; CHECK-THUMB2:         subs r0, r0, r1
-; CHECK-THUMB2:         bx lr
+; CHECK-THUMB2-NEXT:    movw r1, #8995
+; CHECK-THUMB2-NEXT:    subs r0, r0, r1
+; CHECK-THUMB2-NEXT:    bx lr
   %2 = sub i32 %0, 8995
   ret i32 %2
 }
@@ -59,20 +59,20 @@ define i32 @sub2(i32 %0) {
 define i32 @sub3(i32 %0) {
 ; CHECK-ARM-LABEL: sub3:
 ; CHECK-ARM:       @ %bb.0:
-; CHECK-ARM:         ldr r1, .LCPI3_0
-; CHECK-ARM:         add r0, r0, r1
-; CHECK-ARM:         mov pc, lr
-; CHECK-ARM:         .p2align 2
-; CHECK-ARM:       @ %bb.1:
-; CHECK-ARM:         .LCPI3_0:
-; CHECK-ARM:         .long 4292870571 @ 0xffe001ab
+; CHECK-ARM-NEXT:    ldr r1, .LCPI3_0
+; CHECK-ARM-NEXT:    add r0, r0, r1
+; CHECK-ARM-NEXT:    mov pc, lr
+; CHECK-ARM-NEXT:    .p2align 2
+; CHECK-ARM-NEXT:  @ %bb.1:
+; CHECK-ARM-NEXT:  .LCPI3_0:
+; CHECK-ARM-NEXT:    .long 4292870571 @ 0xffe001ab
 ;
 ; CHECK-THUMB2-LABEL: sub3:
 ; CHECK-THUMB2:       @ %bb.0:
-; CHECK-THUMB2:         movw r1, #427
-; CHECK-THUMB2:         movt r1, #65504
-; CHECK-THUMB2:         add r0, r1
-; CHECK-THUMB2:         bx lr
+; CHECK-THUMB2-NEXT:    movw r1, #427
+; CHECK-THUMB2-NEXT:    movt r1, #65504
+; CHECK-THUMB2-NEXT:    add r0, r1
+; CHECK-THUMB2-NEXT:    bx lr
   %2 = sub i32 %0, 2096725
   ret i32 %2
 }
@@ -80,33 +80,33 @@ define i32 @sub3(i32 %0) {
 define i32 @sub4(i32 %0) {
 ; CHECK-ARM-LABEL: sub4:
 ; CHECK-ARM:       @ %bb.0:
-; CHECK-ARM:         ldr r1, .LCPI4_0
-; CHECK-ARM:         dd r0, r0, r1
-; CHECK-ARM:         mov pc, lr
-; CHECK-ARM:         .p2align 2
-; CHECK-ARM:       @ %bb.1:
-; CHECK-ARM:         .LCPI4_0:
-; CHECK-ARM:         .long 4286505147 @ 0xff7ee0bb
+; CHECK-ARM-NEXT:    ldr r1, .LCPI4_0
+; CHECK-ARM-NEXT:    add r0, r0, r1
+; CHECK-ARM-NEXT:    mov pc, lr
+; CHECK-ARM-NEXT:    .p2align 2
+; CHECK-ARM-NEXT:  @ %bb.1:
+; CHECK-ARM-NEXT:  .LCPI4_0:
+; CHECK-ARM-NEXT:    .long 4286505147 @ 0xff7ee0bb
 ;
 ; CHECK-THUMB2-LABEL: sub4:
 ; CHECK-THUMB2:       @ %bb.0:
-; CHECK-THUMB2          movw r1, #57531
-; CHECK-THUMB2          movt r1, #65406
-; CHECK-THUMB2:         add r0, r1
-; CHECK-THUMB2:         bx lr
+; CHECK-THUMB2-NEXT:    movw r1, #57531
+; CHECK-THUMB2-NEXT:    movt r1, #65406
+; CHECK-THUMB2-NEXT:    add r0, r1
+; CHECK-THUMB2-NEXT:    bx lr
   %2 = sub i32 %0, 8462149
   ret i32 %2
 }
 define i32 @add0(i32 %0) {
 ; CHECK-ARM-LABEL: add0:
 ; CHECK-ARM:       @ %bb.0:
-; CHECK-ARM:         add r0, r0, #23
-; CHECK-ARM:         mov pc, lr
+; CHECK-ARM-NEXT:    add r0, r0, #23
+; CHECK-ARM-NEXT:    mov pc, lr
 ;
 ; CHECK-THUMB2-LABEL: add0:
 ; CHECK-THUMB2:       @ %bb.0:
-; CHECK-THUMB2:         adds r0, #23
-; CHECK-THUMB2:         bx lr
+; CHECK-THUMB2-NEXT:    adds r0, #23
+; CHECK-THUMB2-NEXT:    bx lr
   %2 = add i32 %0, 23
   ret i32 %2
 }
@@ -114,20 +114,20 @@ define i32 @add0(i32 %0) {
 define i32 @add1(i32 %0) {
 ; CHECK-ARM-LABEL: add1:
 ; CHECK-ARM:       @ %bb.0:
-; CHECK-ARM          ldr r1, .LCPI4_0
-; CHECK-ARM          add r0, r0, r1
-; CHECK-ARM          mov pc, lr
-; CHECK-ARM          .p2align 2
-; CHECK-ARM        @ %bb.1:
-; CHECK-ARM          .LCPI4_0:
-; CHECK-ARM          .long 131071 @ 0x1ffff
+; CHECK-ARM-NEXT:    ldr r1, .LCPI6_0
+; CHECK-ARM-NEXT:    add r0, r0, r1
+; CHECK-ARM-NEXT:    mov pc, lr
+; CHECK-ARM-NEXT:    .p2align 2
+; CHECK-ARM-NEXT:  @ %bb.1:
+; CHECK-ARM-NEXT:  .LCPI6_0:
+; CHECK-ARM-NEXT:    .long 131071 @ 0x1ffff
 ;
 ; CHECK-THUMB2-LABEL: add1:
 ; CHECK-THUMB2:       @ %bb.0:
-; CHECK-THUMB2:         movw r1, #65535
-; CHECK-THUMB2:         movt r1, #1
-; CHECK-THUMB2:         add r0, r1
-; CHECK-THUMB2:         bx lr
+; CHECK-THUMB2-NEXT:    movw r1, #65535
+; CHECK-THUMB2-NEXT:    movt r1, #1
+; CHECK-THUMB2-NEXT:    add r0, r1
+; CHECK-THUMB2-NEXT:    bx lr
   %2 = add i32 %0, 131071
   ret i32 %2
 }
@@ -135,15 +135,15 @@ define i32 @add1(i32 %0) {
 define i32 @add2(i32 %0) {
 ; CHECK-ARM-LABEL: add2:
 ; CHECK-ARM:       @ %bb.0:
-; CHECK-ARM:         add r0, r0, #8960
-; CHECK-ARM:         add r0, r0, #2293760
-; CHECK-ARM:         mov pc, lr
+; CHECK-ARM-NEXT:    add r0, r0, #8960
+; CHECK-ARM-NEXT:    add r0, r0, #2293760
+; CHECK-ARM-NEXT:    mov pc, lr
 ;
 ; CHECK-THUMB2-LABEL: add2:
 ; CHECK-THUMB2:       @ %bb.0:
-; CHECK-THUMB2:         add.w r0, r0, #2293760
-; CHECK-THUMB2:         add.w r0, r0, #8960
-; CHECK-THUMB2:         bx lr
+; CHECK-THUMB2-NEXT:    add.w r0, r0, #2293760
+; CHECK-THUMB2-NEXT:    add.w r0, r0, #8960
+; CHECK-THUMB2-NEXT:    bx lr
   %2 = add i32 %0, 2302720
   ret i32 %2
 }
@@ -151,20 +151,20 @@ define i32 @add2(i32 %0) {
 define i32 @add3(i32 %0) {
 ; CHECK-ARM-LABEL: add3:
 ; CHECK-ARM:       @ %bb.0:
-; CHECK-ARM:         ldr r1, .LCPI8_0
-; CHECK-ARM:         add r0, r0, r1
-; CHECK-ARM:         mov pc, lr
-; CHECK-ARM:         .p2align 2
-; CHECK-ARM:       @ %bb.1:
-; CHECK-ARM:         .LCPI8_0:
-; CHECK-ARM:         .long 2096725 @ 0x1ffe55
+; CHECK-ARM-NEXT:    ldr r1, .LCPI8_0
+; CHECK-ARM-NEXT:    add r0, r0, r1
+; CHECK-ARM-NEXT:    mov pc, lr
+; CHECK-ARM-NEXT:    .p2align 2
+; CHECK-ARM-NEXT:  @ %bb.1:
+; CHECK-ARM-NEXT:  .LCPI8_0:
+; CHECK-ARM-NEXT:    .long 2096725 @ 0x1ffe55
 ;
 ; CHECK-THUMB2-LABEL: add3:
 ; CHECK-THUMB2:       @ %bb.0:
-; CHECK-THUMB2:         movw r1, #65109
-; CHECK-THUMB2:         movt r1, #31
-; CHECK-THUMB2:         add r0, r1
-; CHECK-THUMB2:         bx lr
+; CHECK-THUMB2-NEXT:    movw r1, #65109
+; CHECK-THUMB2-NEXT:    movt r1, #31
+; CHECK-THUMB2-NEXT:    add r0, r1
+; CHECK-THUMB2-NEXT:    bx lr
   %2 = add i32 %0, 2096725
   ret i32 %2
 }
@@ -172,20 +172,20 @@ define i32 @add3(i32 %0) {
 define i32 @add4(i32 %0) {
 ; CHECK-ARM-LABEL: add4:
 ; CHECK-ARM:       @ %bb.0:
-; CHECK-ARM:         ldr r1, .LCPI9_0
-; CHECK-ARM:         add r0, r0, r1
-; CHECK-ARM:         mov pc, lr
-; CHECK-ARM:         .p2align 2
-; CHECK-ARM:       @ %bb.1:
-; CHECK-ARM:         .LCPI9_0:
-; CHECK-ARM:         .long 8462149 @ 0x811f45
+; CHECK-ARM-NEXT:    ldr r1, .LCPI9_0
+; CHECK-ARM-NEXT:    add r0, r0, r1
+; CHECK-ARM-NEXT:    mov pc, lr
+; CHECK-ARM-NEXT:    .p2align 2
+; CHECK-ARM-NEXT:  @ %bb.1:
+; CHECK-ARM-NEXT:  .LCPI9_0:
+; CHECK-ARM-NEXT:    .long 8462149 @ 0x811f45
 ;
 ; CHECK-THUMB2-LABEL: add4:
 ; CHECK-THUMB2:       @ %bb.0:
-; CHECK-THUMB2:         movw r1, #8005
-; CHECK-THUMB2:         movt r1, #129
-; CHECK-THUMB2:         add r0, r1
-; CHECK-THUMB2:         bx lr
+; CHECK-THUMB2-NEXT:    movw r1, #8005
+; CHECK-THUMB2-NEXT:    movt r1, #129
+; CHECK-THUMB2-NEXT:    add r0, r1
+; CHECK-THUMB2-NEXT:    bx lr
   %2 = add i32 %0, 8462149
   ret i32 %2
 }
@@ -193,15 +193,15 @@ define i32 @add4(i32 %0) {
 define i32 @orr0(i32 %0) {
 ; CHECK-ARM-LABEL: orr0:
 ; CHECK-ARM:       @ %bb.0:
-; CHECK-ARM:         orr r0, r0, #8960
-; CHECK-ARM:         orr r0, r0, #2293760
-; CHECK-ARM:         mov pc, lr
+; CHECK-ARM-NEXT:    orr r0, r0, #8960
+; CHECK-ARM-NEXT:    orr r0, r0, #2293760
+; CHECK-ARM-NEXT:    mov pc, lr
 ;
 ; CHECK-THUMB2-LABEL: orr0:
 ; CHECK-THUMB2:       @ %bb.0:
-; CHECK-THUMB2:         orr r0, r0, #2293760
-; CHECK-THUMB2:         orr r0, r0, #8960
-; CHECK-THUMB2:         bx lr
+; CHECK-THUMB2-NEXT:    orr r0, r0, #2293760
+; CHECK-THUMB2-NEXT:    orr r0, r0, #8960
+; CHECK-THUMB2-NEXT:    bx lr
   %2 = or i32 %0, 2302720
   ret i32 %2
 }
@@ -209,13 +209,13 @@ define i32 @orr0(i32 %0) {
 define i32 @orr1(i32 %0) {
 ; CHECK-ARM-LABEL: orr1:
 ; CHECK-ARM:       @ %bb.0:
-; CHECK-ARM:         orr r0, r0, #23
-; CHECK-ARM:         mov pc, lr
+; CHECK-ARM-NEXT:    orr r0, r0, #23
+; CHECK-ARM-NEXT:    mov pc, lr
 ;
 ; CHECK-THUMB2-LABEL: orr1:
 ; CHECK-THUMB2:       @ %bb.0:
-; CHECK-THUMB2:         orr r0, r0, #23
-; CHECK-THUMB2:         bx lr
+; CHECK-THUMB2-NEXT:    orr r0, r0, #23
+; CHECK-THUMB2-NEXT:    bx lr
   %2 = or i32 %0, 23
   ret i32 %2
 }
@@ -223,20 +223,20 @@ define i32 @orr1(i32 %0) {
 define i32 @orr2(i32 %0) {
 ; CHECK-ARM-LABEL: orr2:
 ; CHECK-ARM:       @ %bb.0:
-; CHECK-ARM:         ldr r1, .LCPI12_0
-; CHECK-ARM:         orr r0, r0, r1
-; CHECK-ARM:         mov pc, lr
-; CHECK-ARM:         .p2align 2
-; CHECK-ARM:       @ %bb.1:
-; CHECK-ARM:         .LCPI12_0:
-; CHECK-ARM:         .long 131071 @ 0x1ffff
+; CHECK-ARM-NEXT:    ldr r1, .LCPI12_0
+; CHECK-ARM-NEXT:    orr r0, r0, r1
+; CHECK-ARM-NEXT:    mov pc, lr
+; CHECK-ARM-NEXT:    .p2align 2
+; CHECK-ARM-NEXT:  @ %bb.1:
+; CHECK-ARM-NEXT:  .LCPI12_0:
+; CHECK-ARM-NEXT:    .long 131071 @ 0x1ffff
 ;
 ; CHECK-THUMB2-LABEL: orr2:
 ; CHECK-THUMB2:       @ %bb.0:
-; CHECK-THUMB2          movs r1, #1
-; CHECK-THUMB2          movt r1, #65534
-; CHECK-THUMB2          orr r0, r1
-; CHECK-THUMB2          bx lr
+; CHECK-THUMB2-NEXT:    movw r1, #65535
+; CHECK-THUMB2-NEXT:    movt r1, #1
+; CHECK-THUMB2-NEXT:    orrs r0, r1
+; CHECK-THUMB2-NEXT:    bx lr
   %2 = or i32 %0, 131071
   ret i32 %2
 }
@@ -244,15 +244,15 @@ define i32 @orr2(i32 %0) {
 define i32 @eor0(i32 %0) {
 ; CHECK-ARM-LABEL: eor0:
 ; CHECK-ARM:       @ %bb.0:
-; CHECK-ARM:         eor r0, r0, #8960
-; CHECK-ARM:         eor r0, r0, #2293760
-; CHECK-ARM:         mov pc, lr
+; CHECK-ARM-NEXT:    eor r0, r0, #8960
+; CHECK-ARM-NEXT:    eor r0, r0, #2293760
+; CHECK-ARM-NEXT:    mov pc, lr
 ;
 ; CHECK-THUMB2-LABEL: eor0:
 ; CHECK-THUMB2:       @ %bb.0:
-; CHECK-THUMB2:         eor r0, r0, #2293760
-; CHECK-THUMB2:         eor r0, r0, #8960
-; CHECK-THUMB2:         bx lr
+; CHECK-THUMB2-NEXT:    eor r0, r0, #2293760
+; CHECK-THUMB2-NEXT:    eor r0, r0, #8960
+; CHECK-THUMB2-NEXT:    bx lr
   %2 = xor i32 %0, 2302720
   ret i32 %2
 }
@@ -260,13 +260,13 @@ define i32 @eor0(i32 %0) {
 define i32 @eor1(i32 %0) {
 ; CHECK-ARM-LABEL: eor1:
 ; CHECK-ARM:       @ %bb.0:
-; CHECK-ARM:         eor r0, r0, #23
-; CHECK-ARM:         mov pc, lr
+; CHECK-ARM-NEXT:    eor r0, r0, #23
+; CHECK-ARM-NEXT:    mov pc, lr
 ;
 ; CHECK-THUMB2-LABEL: eor1:
 ; CHECK-THUMB2:       @ %bb.0:
-; CHECK-THUMB2:         eor r0, r0, #23
-; CHECK-THUMB2:         bx lr
+; CHECK-THUMB2-NEXT:    eor r0, r0, #23
+; CHECK-THUMB2-NEXT:    bx lr
   %2 = xor i32 %0, 23
   ret i32 %2
 }
@@ -274,20 +274,20 @@ define i32 @eor1(i32 %0) {
 define i32 @eor2(i32 %0) {
 ; CHECK-ARM-LABEL: eor2:
 ; CHECK-ARM:       @ %bb.0:
-; CHECK-ARM:         ldr r1, .LCPI15_0
-; CHECK-ARM:         eor r0, r0, r1
-; CHECK-ARM:         mov pc, lr
-; CHECK-ARM:         .p2align 2
-; CHECK-ARM:       @ %bb.1:
-; CHECK-ARM:         .LCPI15_0:
-; CHECK-ARM:         .long 131071 @ 0x1ffff
+; CHECK-ARM-NEXT:    ldr r1, .LCPI15_0
+; CHECK-ARM-NEXT:    eor r0, r0, r1
+; CHECK-ARM-NEXT:    mov pc, lr
+; CHECK-ARM-NEXT:    .p2align 2
+; CHECK-ARM-NEXT:  @ %bb.1:
+; CHECK-ARM-NEXT:  .LCPI15_0:
+; CHECK-ARM-NEXT:    .long 131071 @ 0x1ffff
 ;
 ; CHECK-THUMB2-LABEL: eor2:
 ; CHECK-THUMB2:       @ %bb.0:
-; CHECK-THUMB2          movs r1, #1
-; CHECK-THUMB2          movt r1, #65534
-; CHECK-THUMB2          eor r0, r1
-; CHECK-THUMB2          bx lr
+; CHECK-THUMB2-NEXT:    movw r1, #65535
+; CHECK-THUMB2-NEXT:    movt r1, #1
+; CHECK-THUMB2-NEXT:    eors r0, r1
+; CHECK-THUMB2-NEXT:    bx lr
   %2 = xor i32 %0, 131071
   ret i32 %2
 }

diff --git a/llvm/test/CodeGen/M68k/varargs.ll b/llvm/test/CodeGen/M68k/varargs.ll
index 0fde2ba..0cc7c46 100644 (file)
--- a/llvm/test/CodeGen/M68k/varargs.ll
+++ b/llvm/test/CodeGen/M68k/varargs.ll
@@ -3,7 +3,7 @@
 
 %struct.va_list = type { i8* }
 
-; CHECK-LABEL test:
+; CHECK-LABEL: test:
 define i32 @test(i32 %X, ...) {
   ; Initialize variable argument processing
 ; CHECK-LABEL: test:

diff --git a/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll b/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
index 0fd811f..67397e4 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll
@@ -276,7 +276,7 @@ define dso_local void @fprs_gprs_vecregs() {
 ; ASM32-DAG:     addi 1, 1, 448
 ; ASM32:         blr
 
-; ASM64-LABEL    .fprs_gprs_vecregs:
+; ASM64-LABEL:    .fprs_gprs_vecregs:
 
 ; ASM64:         stdu 1, -544(1)
 ; ASM64-DAG:     li {{[0-9]+}}, 64

diff --git a/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll b/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
index 4721062..45ec735 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-csr-vector.ll
@@ -146,7 +146,7 @@ define dso_local void @fprs_gprs_vecregs() {
 ; ASM32-DAG:     lwz 14, -216(1)                         # 4-byte Folded Reload
 ; ASM32:         blr
 
-; ASM64-LABEL    .fprs_gprs_vecregs:
+; ASM64-LABEL:    .fprs_gprs_vecregs:
 
 ; ASM64-DAG:     std 14, -288(1)                         # 8-byte Folded Spill
 ; ASM64-DAG:     std 25, -200(1)                         # 8-byte Folded Spill

diff --git a/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll b/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
index 38ce370..d8f9a08 100644 (file)
--- a/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
+++ b/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
@@ -756,11 +756,6 @@ define zeroext i8 @getuc2(<16 x i8> %vuc) {
 entry:
   %vecext = extractelement <16 x i8> %vuc, i32 2
   ret i8 %vecext
-
-
-; CHECK-AIX mfvsrd 3, 34
-; CHECK-AIX rldicl 3, 3, 24, 56
-; CHECK-AIX clrldi 3, 3, 56
 }
 
 ; Function Attrs: norecurse nounwind readnone

diff --git a/llvm/test/CodeGen/X86/swift-async-win64.ll b/llvm/test/CodeGen/X86/swift-async-win64.ll
index 823b417..f0c6cb1 100644 (file)
--- a/llvm/test/CodeGen/X86/swift-async-win64.ll
+++ b/llvm/test/CodeGen/X86/swift-async-win64.ll
@@ -16,7 +16,7 @@ define void @simple(i8* swiftasync %context) "frame-pointer"="all" {
 ; CHECK64: btrq    $60, %rbp
 ; CHECK64: retq
 
-; CHECK32-LABEL simple:
+; CHECK32-LABEL: simple:
 ; CHECK32: movl    8(%ebp), [[TMP:%.*]]
 ; CHECK32: movl    [[TMP]], {{.*}}(%ebp)
 

diff --git a/llvm/test/CodeGen/X86/swifttail-async-win64.ll b/llvm/test/CodeGen/X86/swifttail-async-win64.ll
index 429d48b..6791aa7 100644 (file)
--- a/llvm/test/CodeGen/X86/swifttail-async-win64.ll
+++ b/llvm/test/CodeGen/X86/swifttail-async-win64.ll
@@ -29,7 +29,7 @@ define void @calls_swift_async() {
 }
 
 ; CHECK-LABEL: calls_swift_async:
-; CHECK-NOT jmpq has_swift_async
+; CHECK-NOT: jmpq has_swift_async
 
 define swifttailcc void @no_preserve_swiftself() {
   call void asm "","~{r13}"()

diff --git a/llvm/test/DebugInfo/ARM/PR26163.ll b/llvm/test/DebugInfo/ARM/PR26163.ll
index 798812f..daa07c7 100644 (file)
--- a/llvm/test/DebugInfo/ARM/PR26163.ll
+++ b/llvm/test/DebugInfo/ARM/PR26163.ll
@@ -15,7 +15,7 @@
 ; CHECK:      DW_TAG_inlined_subroutine
 ; CHECK:        DW_TAG_variable
 ; CHECK-NEXT:     DW_AT_location (DW_OP_lit0, DW_OP_stack_value, DW_OP_piece 0x4)
-; CHECK-NEXT      DW_AT_name ("i4")
+; CHECK-NEXT:     DW_AT_abstract_origin
 
 ; Created form the following test case (PR26163) with
 ; clang -cc1 -triple armv4t--freebsd11.0-gnueabi -emit-obj -debug-info-kind=standalone -O2 -x c test.c

diff --git a/llvm/test/DebugInfo/fortranSubrangeVar.ll b/llvm/test/DebugInfo/fortranSubrangeVar.ll
index 5cc5f60..377625d 100644 (file)
--- a/llvm/test/DebugInfo/fortranSubrangeVar.ll
+++ b/llvm/test/DebugInfo/fortranSubrangeVar.ll
@@ -15,8 +15,8 @@
 ; CHECK-SAME: DW_OP_plus_uconst 0x50
 ; CHECK:     DW_TAG_subrange_type
 ; CHECK:                  DW_AT_lower_bound     ([[DIE3]])
-; CHEK-NEXT:              DW_AT_upper_bound     ([[DIE2]])
-; CHECK-NEXT              DW_AT_byte_stride     ([[DIE1]])
+; CHECK-NEXT:              DW_AT_upper_bound     ([[DIE2]])
+; CHECK-NEXT:              DW_AT_byte_stride     ([[DIE1]])
 
 
 ; ModuleID = 'fortsubrange.ll'

diff --git a/llvm/test/Transforms/FunctionAttrs/willreturn-callsites.ll b/llvm/test/Transforms/FunctionAttrs/willreturn-callsites.ll
index d070763..b1e20cf 100644 (file)
--- a/llvm/test/Transforms/FunctionAttrs/willreturn-callsites.ll
+++ b/llvm/test/Transforms/FunctionAttrs/willreturn-callsites.ll
@@ -25,7 +25,7 @@ define void @test_fn_willreturn(i32* %ptr) willreturn {
 ; CHECK: Function Attrs: mustprogress willreturn
 ; CHECK-LABEL: @test_fn_willreturn(
 ; CHECK-NOT:     call void @decl_readonly() #
-; CHECK-NOT :    call void @decl_readnone() #
+; CHECK-NOT:    call void @decl_readnone() #
 ; CHECK-NOT:     call void @decl_unknown() #
 ; CHECK-NOT:     call void @decl_argmemonly(i32* [[PTR:%.*]]) #
 ; CHECK:         ret void

diff --git a/llvm/test/Transforms/InferAddressSpaces/NVPTX/clone_constexpr.ll b/llvm/test/Transforms/InferAddressSpaces/NVPTX/clone_constexpr.ll
index 07593f1..15fa984 100644 (file)
--- a/llvm/test/Transforms/InferAddressSpaces/NVPTX/clone_constexpr.ll
+++ b/llvm/test/Transforms/InferAddressSpaces/NVPTX/clone_constexpr.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -mtriple=nvptx64-nvidia-cuda -infer-address-spaces %s | FileCheck %s
 
 %struct.S = type { [5 x i32] }
@@ -6,16 +7,18 @@ $g1 = comdat any
 
 @g1 = linkonce_odr addrspace(3) global %struct.S zeroinitializer, comdat, align 4
 
-; CHECK-LABEL: @foo(
-; CHECK:  %x0 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x() #2
-; CHECK:  %idxprom.i = zext i32 %x0 to i64
-; CHECK:  %arrayidx.i = getelementptr %struct.S, %struct.S* addrspacecast (%struct.S addrspace(3)* @g1 to %struct.S*), i64 0, i32 0, i64 %idxprom.i
-; CHECK:  tail call void @f1(i32* %arrayidx.i, i32 undef) #0
-; CHECK:  %x1 = load i32, i32 addrspace(3)* getelementptr inbounds (%struct.S, %struct.S addrspace(3)* @g1, i64 0, i32 0, i64 0), align 4
-; CHECK:  %L.sroa.0.0.insert.ext.i = zext i32 %x1 to i64
-; CHECK:  tail call void @f2(i64* null, i64 %L.sroa.0.0.insert.ext.i) #0
-; CHECK:  ret void
 define void @foo() local_unnamed_addr #0 {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[X0:%.*]] = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x() #[[ATTR2:[0-9]+]]
+; CHECK-NEXT:    [[IDXPROM_I:%.*]] = zext i32 [[X0]] to i64
+; CHECK-NEXT:    [[ARRAYIDX_I:%.*]] = getelementptr [[STRUCT_S:%.*]], %struct.S* addrspacecast ([[STRUCT_S]] addrspace(3)* @g1 to %struct.S*), i64 0, i32 0, i64 [[IDXPROM_I]]
+; CHECK-NEXT:    tail call void @f1(i32* [[ARRAYIDX_I]], i32 undef) #[[ATTR0:[0-9]+]]
+; CHECK-NEXT:    [[X1:%.*]] = load i32, i32 addrspace(3)* getelementptr inbounds ([[STRUCT_S]], [[STRUCT_S]] addrspace(3)* @g1, i64 0, i32 0, i64 0), align 4
+; CHECK-NEXT:    [[L_SROA_0_0_INSERT_EXT_I:%.*]] = zext i32 [[X1]] to i64
+; CHECK-NEXT:    tail call void @f2(i64* null, i64 [[L_SROA_0_0_INSERT_EXT_I]]) #[[ATTR0]]
+; CHECK-NEXT:    ret void
+;
 entry:
   %x0 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x() #2
   %idxprom.i = zext i32 %x0 to i64
@@ -35,18 +38,12 @@ declare i32 @llvm.nvvm.read.ptx.sreg.tid.x() #1
 ; https://bugs.llvm.org/show_bug.cgi?id=51099
 @g2 = internal addrspace(3) global [128 x i8] undef, align 1
 
-; CHECK-LABEL: @complex_ce(
-; CHECK: %0 = load float, float addrspace(3)* bitcast
-; CHECK-SAME:   i8 addrspace(3)* getelementptr (i8,
-; CHECK-SAME:     i8 addrspace(3)* getelementptr inbounds ([128 x i8], [128 x i8] addrspace(3)* @g2, i64 0, i64 0),
-; CHECK-SAME:     i64 sub (
-; CHECK-SAME        i64 ptrtoint (
-; CHECK-SAME          i8 addrspace(3)* getelementptr inbounds ([128 x i8], [128 x i8] addrspace(3)* @g2, i64 0, i64 123) to i64),
-; CHECK-SAME:       i64 ptrtoint (
-; CHECK-SAME:         i8 addrspace(3)* getelementptr inbounds ([128 x i8], [128 x i8] addrspace(3)* @g2, i64 2, i64 0) to i64)))
-; CHECK-SAME:   to float addrspace(3)*)
-; Function Attrs: norecurse nounwind
 define float @complex_ce(i8* nocapture readnone %a, i8* nocapture readnone %b, i8* nocapture readnone %c) local_unnamed_addr #0 {
+; CHECK-LABEL: @complex_ce(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load float, float addrspace(3)* bitcast (i8 addrspace(3)* getelementptr (i8, i8 addrspace(3)* getelementptr inbounds ([128 x i8], [128 x i8] addrspace(3)* @g2, i64 0, i64 0), i64 sub (i64 ptrtoint (i8 addrspace(3)* getelementptr inbounds ([128 x i8], [128 x i8] addrspace(3)* @g2, i64 0, i64 123) to i64), i64 ptrtoint (i8 addrspace(3)* getelementptr inbounds ([128 x i8], [128 x i8] addrspace(3)* @g2, i64 2, i64 0) to i64))) to float addrspace(3)*), align 4
+; CHECK-NEXT:    ret float [[TMP0]]
+;
 entry:
   %0 = load float, float* bitcast (
        i8* getelementptr (