Summary: Target specific method encapsulated into the Target Lowering Info.
Reviewers: rampitec, vpykhtin
Reviewed By: rampitec
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70085
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
+#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
#include "llvm/CodeGen/DAGCombine.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
return RC;
}
- /// Allows target to decide about the register class of the
- /// specific value that is live outside the defining block.
- /// Returns true if the value needs uniform register class.
- virtual bool requiresUniformRegister(MachineFunction &MF,
- const Value *) const {
- return false;
+ /// Allows target to decide about the divergence of the
+ /// specific value. Base class implementation returns true
+ /// if the Divergece Analysis exists and reports value as divergent.
+ virtual bool isDivergent(const LegacyDivergenceAnalysis *DA,
+ MachineFunction &MF, const Value *V) const {
+ return DA && DA->isDivergent(V);
}
/// Return the 'representative' register class for the specified value
}
Register FunctionLoweringInfo::CreateRegs(const Value *V) {
- return CreateRegs(V->getType(), DA && DA->isDivergent(V) &&
- !TLI->requiresUniformRegister(*MF, V));
+ return CreateRegs(V->getType(), TLI->isDivergent(DA, *MF, V));
}
/// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
return RC;
}
+bool SITargetLowering::isDivergent(const LegacyDivergenceAnalysis *DA,
+ MachineFunction &MF, const Value *V) const {
+ return !requiresUniformRegister(MF, V) &&
+ TargetLoweringBase::isDivergent(DA, MF, V);
+}
+
// FIXME: This is a workaround for DivergenceAnalysis not understanding always
// uniform values (as produced by the mask results of control flow intrinsics)
// used outside of divergent blocks. The phi users need to also be treated as
virtual const TargetRegisterClass *
getRegClassFor(MVT VT, bool isDivergent) const override;
- virtual bool requiresUniformRegister(MachineFunction &MF,
- const Value *V) const override;
+ virtual bool isDivergent(const LegacyDivergenceAnalysis *DA,
+ MachineFunction &MF, const Value *V) const override;
+ bool requiresUniformRegister(MachineFunction &MF, const Value *V) const;
Align getPrefLoopAlignment(MachineLoop *ML) const override;
void allocateHSAUserSGPRs(CCState &CCInfo,