ARM:AM33XX: Fix ddr and timer register offset

This patch is added to update incorrect ddr and timer
register offset.

Signed-off-by: Chandan Nath <chandan.nath@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>

diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 2d6d359..78db3a5 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -26,7 +26,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-struct timer_reg *timerreg = (struct timer_reg *)DM_TIMER2_BASE;
+struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
 
 /*
  * early system init of muxing and clocks.
@@ -55,12 +55,12 @@ void s_init(u32 in_ddr)
 void init_timer(void)
 {
        /* Reset the Timer */
-       writel(0x2, (&timerreg->tsicrreg));
+       writel(0x2, (&timer_base->tscir));
 
        /* Wait until the reset is done */
-       while (readl(&timerreg->tiocpcfgreg) & 1)
+       while (readl(&timer_base->tiocp_cfg) & 1)
                ;
 
        /* Start the Timer */
-       writel(0x1, (&timerreg->tclrreg));
+       writel(0x1, (&timer_base->tclr));
 }

diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index 4ca6c45..7070e7d 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -101,6 +101,9 @@ static void enable_per_clocks(void)
        while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
                ;
 
+       /* Select the Master osc 24 MHZ as Timer2 clock source */
+       writel(0x1, &cmdpll->clktimer2clk);
+
        /* UART0 */
        writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
        while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)

diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index d18750a..25558a2 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -108,22 +108,36 @@ struct cm_perpll {
        unsigned int l3sclkstctrl;      /* offset 0x04 */
        unsigned int l4fwclkstctrl;     /* offset 0x08 */
        unsigned int l3clkstctrl;       /* offset 0x0c */
-       unsigned int resv1[6];
+       unsigned int resv1;
+       unsigned int cpgmac0clkctrl;    /* offset 0x14 */
+       unsigned int resv2[4];
        unsigned int emifclkctrl;       /* offset 0x28 */
        unsigned int ocmcramclkctrl;    /* offset 0x2c */
-       unsigned int resv2[12];
+       unsigned int gpmcclkctrl;       /* offset 0x30 */
+       unsigned int resv3[2];
+       unsigned int mmc0clkctrl;       /* offset 0x3C */
+       unsigned int elmclkctrl;        /* offset 0x40 */
+       unsigned int i2c2clkctrl;       /* offset 0x44 */
+       unsigned int i2c1clkctrl;       /* offset 0x48 */
+       unsigned int spi0clkctrl;       /* offset 0x4C */
+       unsigned int spi1clkctrl;       /* offset 0x50 */
+       unsigned int resv4[3];
        unsigned int l4lsclkctrl;       /* offset 0x60 */
        unsigned int l4fwclkctrl;       /* offset 0x64 */
-       unsigned int resv3[6];
+       unsigned int resv5[6];
        unsigned int timer2clkctrl;     /* offset 0x80 */
-       unsigned int resv4[19];
+       unsigned int resv6[11];
+       unsigned int gpio2clkctrl;      /* offset 0xB0 */
+       unsigned int resv7[7];
        unsigned int emiffwclkctrl;     /* offset 0xD0 */
-       unsigned int resv5[2];
+       unsigned int resv8[2];
        unsigned int l3instrclkctrl;    /* offset 0xDC */
        unsigned int l3clkctrl;         /* Offset 0xE0 */
-       unsigned int resv6[14];
+       unsigned int resv9[14];
        unsigned int l4hsclkstctrl;     /* offset 0x11C */
        unsigned int l4hsclkctrl;       /* offset 0x120 */
+       unsigned int resv10[8];
+       unsigned int cpswclkctrl;       /* offset 0x144 */
 };
 
 /* Encapsulating Display pll registers */
@@ -158,24 +172,12 @@ struct wd_timer {
        unsigned int wdt_unfr;  /* offset 0x100 */
 };
 
-/* Timer Registers */
-struct timer_reg {
-       unsigned int resv1[4];
-       unsigned int tiocpcfgreg;       /* offset 0x10 */
-       unsigned int resv2[9];
-       unsigned int tclrreg;           /* offset 0x38 */
-       unsigned int tcrrreg;           /* offset 0x3C */
-       unsigned int tldrreg;           /* offset 0x40 */
-       unsigned int resv3[4];
-       unsigned int tsicrreg;          /* offset 0x54 */
-};
-
 /* Timer 32 bit registers */
 struct gptimer {
        unsigned int tidr;              /* offset 0x00 */
-       unsigned int res1[0xc];
+       unsigned char res1[12];
        unsigned int tiocp_cfg;         /* offset 0x10 */
-       unsigned int res2[0xc];
+       unsigned char res2[12];
        unsigned int tier;              /* offset 0x20 */
        unsigned int tistatr;           /* offset 0x24 */
        unsigned int tistat;            /* offset 0x28 */

diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 9638b4c..ba6b59b 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -76,7 +76,7 @@ struct emif_regs {
        unsigned int sdrmcsr;           /* offset 0x3C */
        unsigned int res2[8];
        unsigned int sdritr;            /* offset 0x60 */
-       unsigned int res3[20];
+       unsigned int res3[32];
        unsigned int ddrphycr;          /* offset 0xE4 */
        unsigned int ddrphycsr;         /* offset 0xE8 */
        unsigned int ddrphycr2;         /* offset 0xEC */
@@ -161,10 +161,10 @@ struct ddr_regs {
        unsigned int dt0wiratio1;       /* offset 0x0F4 */
        unsigned int dt0giratio0;       /* offset 0x0FC */
        unsigned int dt0giratio1;       /* offset 0x100 */
-       unsigned int resv6[2];
+       unsigned int resv6[1];
        unsigned int dt0fwsratio0;      /* offset 0x108 */
        unsigned int dt0fwsratio1;      /* offset 0x10C */
-       unsigned int resv7[5];
+       unsigned int resv7[4];
        unsigned int dt0wrsratio0;      /* offset 0x120 */
        unsigned int dt0wrsratio1;      /* offset 0x124 */
        unsigned int resv8[3];