return true;
} else if (nir->info.stage == MESA_SHADER_TASK) {
ac_nir_lower_task_outputs_to_mem(nir, AC_TASK_PAYLOAD_ENTRY_BYTES, device->physical_device->task_info.num_entries,
- false);
+ info->cs.has_query);
return true;
} else if (nir->info.stage == MESA_SHADER_MESH) {
ac_nir_lower_mesh_inputs_to_mem(nir, AC_TASK_PAYLOAD_ENTRY_BYTES, device->physical_device->task_info.num_entries);
bool use_perf_counters = false;
bool use_dgc = false;
bool smooth_lines = false;
+ bool mesh_shader_queries = false;
/* Check enabled features */
if (pCreateInfo->pEnabledFeatures) {
smooth_lines = true;
break;
}
+ case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MESH_SHADER_FEATURES_EXT: {
+ const VkPhysicalDeviceMeshShaderFeaturesEXT *features = (const void *)ext;
+ if (features->meshShaderQueries)
+ mesh_shader_queries = true;
+ break;
+ }
default:
break;
}
device->primitives_generated_query = primitives_generated_query;
device->uses_device_generated_commands = use_dgc;
device->smooth_lines = smooth_lines;
+ device->mesh_shader_queries = mesh_shader_queries;
radv_init_shader_arenas(device);
}
}
+ key.mesh_shader_queries = device->mesh_shader_queries;
+
return key;
}
/* Whether smooth lines is enabled. */
bool smooth_lines;
+ /* Whether mesh shader queries are enabled. */
+ bool mesh_shader_queries;
+
bool uses_shadow_regs;
struct hash_table *rt_handles;
bool scratch_ring = false;
NIR_PASS_V(nir, ac_nir_lower_ngg_ms, options.gfx_level, options.clipdist_enable_mask,
options.vs_output_param_offset, options.has_param_exports, &scratch_ring, info->wave_size,
- pl_key->has_multiview_view_index, false);
+ pl_key->has_multiview_view_index, info->ms.has_query);
ngg_stage->info.ms.needs_ms_scratch_ring = scratch_ring;
} else {
unreachable("invalid SW stage passed to radv_lower_ngg");
uint32_t tex_non_uniform : 1;
uint32_t enable_remove_point_size : 1;
uint32_t unknown_rast_prim : 1;
+ uint32_t mesh_shader_queries : 1;
uint32_t vertex_robustness1 : 1;
bool uses_rt;
bool uses_full_subgroups;
bool linear_taskmesh_dispatch;
+ bool has_query; /* Task shader only */
bool regalloc_hang_bug;
} cs;
enum mesa_prim output_prim;
bool needs_ms_scratch_ring;
bool has_task; /* If mesh shader is used together with a task shader. */
+ bool has_query;
} ms;
struct radv_streamout_info so;
}
static void
-gather_shader_info_mesh(const nir_shader *nir, struct radv_shader_info *info)
+gather_shader_info_mesh(const nir_shader *nir, const struct radv_pipeline_key *pipeline_key,
+ struct radv_shader_info *info)
{
struct gfx10_ngg_info *ngg_info = &info->ngg_info;
unsigned api_workgroup_size = ac_compute_cs_workgroup_size(nir->info.workgroup_size, false, UINT32_MAX);
info->workgroup_size = MAX2(min_ngg_workgroup_size, api_workgroup_size);
+
+ info->ms.has_query = pipeline_key->mesh_shader_queries;
}
static void
}
static void
-gather_shader_info_task(const nir_shader *nir, struct radv_shader_info *info)
+gather_shader_info_task(const nir_shader *nir, const struct radv_pipeline_key *pipeline_key,
+ struct radv_shader_info *info)
{
/* Task shaders always need these for the I/O lowering even if the API shader doesn't actually
* use them.
*/
info->cs.linear_taskmesh_dispatch =
nir->info.mesh.ts_mesh_dispatch_dimensions[1] == 1 && nir->info.mesh.ts_mesh_dispatch_dimensions[2] == 1;
+
+ info->cs.has_query = pipeline_key->mesh_shader_queries;
}
static uint32_t
gather_shader_info_cs(device, nir, pipeline_key, info);
break;
case MESA_SHADER_TASK:
- gather_shader_info_task(nir, info);
+ gather_shader_info_task(nir, pipeline_key, info);
break;
case MESA_SHADER_FRAGMENT:
gather_shader_info_fs(device, nir, pipeline_key, info);
gather_shader_info_vs(device, nir, pipeline_key, info);
break;
case MESA_SHADER_MESH:
- gather_shader_info_mesh(nir, info);
+ gather_shader_info_mesh(nir, pipeline_key, info);
break;
default:
if (gl_shader_stage_is_rt(nir->info.stage))