Only for 83xx systems. If specified, then DDR should
be configured using CS0 and CS1 instead of CS2 and CS3.
-- CONFIG_ETHER_ON_FEC[12]
- Define to enable FEC[12] on a 8xx series processor.
-
-- CONFIG_FEC[12]_PHY
- Define to the hardcoded PHY address which corresponds
- to the given FEC; i. e.
- #define CONFIG_FEC1_PHY 4
- means that the PHY with address 4 is connected to FEC1
-
- When set to -1, means to probe for first available.
-
-- CONFIG_FEC[12]_PHY_NORXERR
- The PHY does not have a RXERR line (RMII only).
- (so program the FEC to ignore it).
-
- CONFIG_RMII
Enable RMII mode for all FECs.
Note that this is a global option, we can't
extra-y += traps.o
obj-y += cpu.o
obj-y += cpu_init.o
-obj-y += fec.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_CMD_IMMAP) += immap.o
obj-y += interrupts.o
*/
int cpu_eth_init(bd_t *bis)
{
-#if defined(FEC_ENET)
+#if defined(CONFIG_MPC8XX_FEC)
fec_initialize(bis);
#endif
return 0;
This driver implements support for the Ethernet AVB block in
Renesas M3 and H3 SoCs.
+config MPC8XX_FEC
+ bool "Fast Ethernet Controller on MPC8XX"
+ depends on 8xx
+ select MII
+ help
+ This driver implements support for the Fast Ethernet Controller
+ on MPC8XX
+
+config ETHER_ON_FEC1
+ bool "FEC1"
+ depends on MPC8XX_FEC
+ default y
+
+config FEC1_PHY
+ int "FEC1 PHY"
+ depends on ETHER_ON_FEC1
+ default -1
+ help
+ Define to the hardcoded PHY address which corresponds
+ to the given FEC; i. e.
+ #define CONFIG_FEC1_PHY 4
+ means that the PHY with address 4 is connected to FEC1
+
+ When set to -1, means to probe for first available.
+
+config PHY_NORXERR
+ bool "PHY_NORXERR"
+ depends on ETHER_ON_FEC1
+ default n
+ help
+ The PHY does not have a RXERR line (RMII only).
+ (so program the FEC to ignore it).
+
+config ETHER_ON_FEC2
+ bool "FEC2"
+ depends on MPC8XX_FEC && MPC885
+ default y
+
+config FEC2_PHY
+ int "FEC2 PHY"
+ depends on ETHER_ON_FEC2
+ default -1
+ help
+ Define to the hardcoded PHY address which corresponds
+ to the given FEC; i. e.
+ #define CONFIG_FEC1_PHY 4
+ means that the PHY with address 4 is connected to FEC1
+
+ When set to -1, means to probe for first available.
+
+config FEC2_PHY_NORXERR
+ bool "PHY_NORXERR"
+ depends on ETHER_ON_FEC2
+ default n
+ help
+ The PHY does not have a RXERR line (RMII only).
+ (so program the FEC to ignore it).
+
endif # NETDEVICES
obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
obj-$(CONFIG_MACB) += macb.o
obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
+obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o
obj-$(CONFIG_MVGBE) += mvgbe.o
obj-$(CONFIG_MVNETA) += mvneta.o
obj-$(CONFIG_MVPP2) += mvpp2.o
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_CMD_NET) && \
- (defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2))
-
-/* compatibility test, if only FEC_ENET defined assume ETHER on FEC1 */
-#if defined(FEC_ENET) && !defined(CONFIG_ETHER_ON_FEC1) && !defined(CONFIG_ETHER_ON_FEC2)
-#define CONFIG_ETHER_ON_FEC1 1
-#endif
-
/* define WANT_MII when MII support is required */
#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY)
#define WANT_MII
{
0,
offsetof(immap_t, im_cpm.cp_fec1),
-#if defined(CONFIG_FEC1_PHY)
CONFIG_FEC1_PHY,
-#else
- -1, /* discover */
-#endif
-1,
0,
{
1,
offsetof(immap_t, im_cpm.cp_fec2),
-#if defined(CONFIG_FEC2_PHY)
CONFIG_FEC2_PHY,
-#else
- -1,
-#endif
-1,
0,
},
return 0;
}
#endif
-
-#endif
CONFIG_ETHER_ON_FCC1
CONFIG_ETHER_ON_FCC2
CONFIG_ETHER_ON_FCC3
-CONFIG_ETHER_ON_FEC1
-CONFIG_ETHER_ON_FEC2
CONFIG_ETHPRIME
CONFIG_ETH_BUFSIZE
CONFIG_ETH_RXSIZE
CONFIG_FEATURE_SH_EXTRA_QUIET
CONFIG_FEATURE_SH_FANCY_PROMPT
CONFIG_FEATURE_SH_STANDALONE_SHELL
-CONFIG_FEC1_PHY
-CONFIG_FEC2_PHY
CONFIG_FEC_ENET_DEV
CONFIG_FEC_FIXED_SPEED
CONFIG_FEC_MXC_25M_REF_CLK