arm64: dts: qcom: msm8998: Fix cache nodes

The msm8998 cache nodes have some issues. First, L1 caches are described
within cpu nodes, not as separate nodes. The 'next-level-cache' property
is of course in the correct location, otherwise the cache hierarchy
walking would not work. Remove all the L1 cache nodes.

Second, 'arm,arch-cache' is not a documented compatible string. "cache"
is a sufficient compatible string for the Arm architected caches.

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211217211136.3536443-1-robh@kernel.org

diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 453a049f693db42ac16d9e05774c1d42956d1cd6..2fda21e810c966c8eb89eeac60972027a153bb8f 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -138,15 +138,9 @@
                        cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
                        next-level-cache = <&L2_0>;
                        L2_0: l2-cache {
-                               compatible = "arm,arch-cache";
+                               compatible = "cache";
                                cache-level = <2>;
                        };
-                       L1_I_0: l1-icache {
-                               compatible = "arm,arch-cache";
-                       };
-                       L1_D_0: l1-dcache {
-                               compatible = "arm,arch-cache";
-                       };
                };
 
                CPU1: cpu@1 {
@@ -157,12 +151,6 @@
                        capacity-dmips-mhz = <1024>;
                        cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
                        next-level-cache = <&L2_0>;
-                       L1_I_1: l1-icache {
-                               compatible = "arm,arch-cache";
-                       };
-                       L1_D_1: l1-dcache {
-                               compatible = "arm,arch-cache";
-                       };
                };
 
                CPU2: cpu@2 {
@@ -173,12 +161,6 @@
                        capacity-dmips-mhz = <1024>;
                        cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
                        next-level-cache = <&L2_0>;
-                       L1_I_2: l1-icache {
-                               compatible = "arm,arch-cache";
-                       };
-                       L1_D_2: l1-dcache {
-                               compatible = "arm,arch-cache";
-                       };
                };
 
                CPU3: cpu@3 {
@@ -189,12 +171,6 @@
                        capacity-dmips-mhz = <1024>;
                        cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
                        next-level-cache = <&L2_0>;
-                       L1_I_3: l1-icache {
-                               compatible = "arm,arch-cache";
-                       };
-                       L1_D_3: l1-dcache {
-                               compatible = "arm,arch-cache";
-                       };
                };
 
                CPU4: cpu@100 {
@@ -206,15 +182,9 @@
                        cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
                        next-level-cache = <&L2_1>;
                        L2_1: l2-cache {
-                               compatible = "arm,arch-cache";
+                               compatible = "cache";
                                cache-level = <2>;
                        };
-                       L1_I_100: l1-icache {
-                               compatible = "arm,arch-cache";
-                       };
-                       L1_D_100: l1-dcache {
-                               compatible = "arm,arch-cache";
-                       };
                };
 
                CPU5: cpu@101 {
@@ -225,12 +195,6 @@
                        capacity-dmips-mhz = <1536>;
                        cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
                        next-level-cache = <&L2_1>;
-                       L1_I_101: l1-icache {
-                               compatible = "arm,arch-cache";
-                       };
-                       L1_D_101: l1-dcache {
-                               compatible = "arm,arch-cache";
-                       };
                };
 
                CPU6: cpu@102 {
@@ -241,12 +205,6 @@
                        capacity-dmips-mhz = <1536>;
                        cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
                        next-level-cache = <&L2_1>;
-                       L1_I_102: l1-icache {
-                               compatible = "arm,arch-cache";
-                       };
-                       L1_D_102: l1-dcache {
-                               compatible = "arm,arch-cache";
-                       };
                };
 
                CPU7: cpu@103 {
@@ -257,12 +215,6 @@
                        capacity-dmips-mhz = <1536>;
                        cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
                        next-level-cache = <&L2_1>;
-                       L1_I_103: l1-icache {
-                               compatible = "arm,arch-cache";
-                       };
-                       L1_D_103: l1-dcache {
-                               compatible = "arm,arch-cache";
-                       };
                };
 
                cpu-map {