# v8-m/v8.1-m VLLDM errata.
define feature quirk_vlldm
+# AES errata on some Cortex-A parts
+define feature quirk_aes_1742098
+
# Don't use .cpu assembly directive
define feature quirk_no_asmcpu
# architectures.
# xscale isn't really a 'quirk', but it isn't an architecture either and we
# need to ignore it for matching purposes.
-define fgroup ALL_QUIRKS quirk_no_volatile_ce quirk_armv6kz quirk_cm3_ldrd quirk_vlldm xscale quirk_no_asmcpu
+define fgroup ALL_QUIRKS quirk_no_volatile_ce quirk_armv6kz quirk_cm3_ldrd quirk_vlldm xscale quirk_no_asmcpu quirk_aes_1742098
define fgroup IGNORE_FOR_MULTILIB cdecp0 cdecp1 cdecp2 cdecp3 cdecp4 cdecp5 cdecp6 cdecp7
cname cortexa57
tune flags LDSCHED
architecture armv8-a+crc+simd
+ isa quirk_aes_1742098
option crypto add FP_ARMv8 CRYPTO
costs cortex_a57
vendor 41
tune for cortex-a57
tune flags LDSCHED
architecture armv8-a+crc+simd
+ isa quirk_aes_1742098
option crypto add FP_ARMv8 CRYPTO
costs cortex_a57
vendor 41
tune for cortex-a53
tune flags LDSCHED
architecture armv8-a+crc+simd
+ isa quirk_aes_1742098
option crypto add FP_ARMv8 CRYPTO
costs cortex_a57
end cpu cortex-a57.cortex-a53
tune for cortex-a53
tune flags LDSCHED
architecture armv8-a+crc+simd
+ isa quirk_aes_1742098
option crypto add FP_ARMv8 CRYPTO
costs cortex_a57
end cpu cortex-a72.cortex-a53
fix_vlldm = 0;
}
+ /* Enable fix_aes by default if required. */
+ if (fix_aes_erratum_1742098 == 2)
+ {
+ if (bitmap_bit_p (arm_active_target.isa, isa_bit_quirk_aes_1742098))
+ fix_aes_erratum_1742098 = 1;
+ else
+ fix_aes_erratum_1742098 = 0;
+ }
+
/* Hot/Cold partitioning is not currently supported, since we can't
handle literal pool placement in that case. */
if (flag_reorder_blocks_and_partition)
Target Var(fix_vlldm) Init(2)
Mitigate issues with VLLDM on some M-profile devices (CVE-2021-35465).
+mfix-cortex-a57-aes-1742098
+Target Var(fix_aes_erratum_1742098) Init(2) Save
+Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
+Arm erratum #1742098
+
+mfix-cortex-a72-aes-1655431
+Target Alias(mfix-cortex-a57-aes-1742098)
+Mitigate issues with AES instructions on Cortex-A57 and Cortex-A72.
+Arm erratum #1655431
+
munaligned-access
Target Var(unaligned_access) Init(2) Save
Enable unaligned word and halfword accesses to packed data.
-mtp=@var{name} -mtls-dialect=@var{dialect} @gol
-mword-relocations @gol
-mfix-cortex-m3-ldrd @gol
+-mfix-cortex-a57-aes-1742098 @gol
+-mfix-cortex-a72-aes-1655431 @gol
-munaligned-access @gol
-mneon-for-64bits @gol
-mslow-flash-data @gol
generating these instructions. This option is enabled by default when
@option{-mcpu=cortex-m3} is specified.
+@item -mfix-cortex-a57-aes-1742098
+@itemx -mno-fix-cortex-a57-aes-1742098
+@itemx -mfix-cortex-a72-aes-1655431
+@itemx -mno-fix-cortex-a72-aes-1655431
+Enable (disable) mitigation for an erratum on Cortex-A57 and
+Cortex-A72 that affects the AES cryptographic instructions. This
+option is enabled by default when either @option{-mcpu=cortex-a57} or
+@option{-mcpu=cortex-a72} is specified.
+
@item -munaligned-access
@itemx -mno-unaligned-access
@opindex munaligned-access