clk: rockchip: use clock ids for PCLK_DPHYRX and PCLK_DPHYTX0 on rk3368
authorHeiko Stuebner <heiko.stuebner@theobroma-systems.com>
Fri, 5 Feb 2021 11:04:59 +0000 (12:04 +0100)
committerHeiko Stuebner <heiko@sntech.de>
Sat, 6 Feb 2021 00:05:04 +0000 (01:05 +0100)
Export the clocks via the newly added clock-ids.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Link: https://lore.kernel.org/r/20210205110502.1850669-2-heiko@sntech.de
drivers/clk/rockchip/clk-rk3368.c

index 5544334..76fb041 100644 (file)
@@ -818,8 +818,8 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
         * pclk_vio gates
         * pclk_vio comes from the exactly same source as hclk_vio
         */
-       GATE(0, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
-       GATE(0, "pclk_dphytx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
+       GATE(PCLK_DPHYRX, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
+       GATE(PCLK_DPHYTX0, "pclk_dphytx0", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
 
        /* pclk_pd_pmu gates */
        GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 5, GFLAGS),