fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
-#if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
+#if defined(TARGET_SPARC) || defined(TARGET_PPC)
cpu_reset(ENV_GET_CPU(env));
#endif
thread_env = env;
val |= E1000_ICR_INT_ASSERTED;
}
s->mac_reg[ICR] = val;
+
+ /*
+ * Make sure ICR and ICS registers have the same value.
+ * The spec says that the ICS register is write-only. However in practice,
+ * on real hardware ICS is readable, and for reads it has the same value as
+ * ICR (except that ICS does not have the clear on read behaviour of ICR).
+ *
+ * The VxWorks PRO/1000 driver uses this behaviour.
+ */
s->mac_reg[ICS] = val;
+
qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
}
void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx);
+PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin);
void ich9_lpc_pm_init(PCIDevice *pci_lpc, qemu_irq cmos_s3);
PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus);
i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
ich9_cc_addr_len(&addr, &len);
memcpy(lpc->chip_config + addr, &val, len);
+ pci_bus_fire_intx_routing_notifier(lpc->d.bus);
ich9_cc_update(lpc);
}
return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx];
}
+PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
+{
+ ICH9LPCState *lpc = opaque;
+ PCIINTxRoute route;
+ int pic_irq;
+ int pic_dis;
+
+ assert(0 <= pirq_pin);
+ assert(pirq_pin < ICH9_LPC_NB_PIRQS);
+
+ route.mode = PCI_INTX_ENABLED;
+ ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis);
+ if (!pic_dis) {
+ if (pic_irq < ICH9_LPC_PIC_NUM_PINS) {
+ route.irq = pic_irq;
+ } else {
+ route.mode = PCI_INTX_DISABLED;
+ route.irq = -1;
+ }
+ } else {
+ route.irq = ich9_pirq_to_gsi(pirq_pin);
+ }
+
+ return route;
+}
+
static int ich9_lpc_sci_irq(ICH9LPCState *lpc)
{
switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] &
if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) {
ich9_lpc_rcba_update(lpc, rbca_old);
}
+ if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) {
+ pci_bus_fire_intx_routing_notifier(lpc->d.bus);
+ }
+ if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) {
+ pci_bus_fire_intx_routing_notifier(lpc->d.bus);
+ }
}
static void ich9_lpc_reset(DeviceState *qdev)
static void handle_a20_line_change(void *opaque, int irq, int level)
{
- CPUX86State *cpu = opaque;
+ X86CPU *cpu = opaque;
/* XXX: send to all CPUs ? */
/* XXX: add logic to handle multiple A20 line sources */
- cpu_x86_set_a20(cpu, level);
+ x86_cpu_set_a20(cpu, level);
}
int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
}
}
- a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
+ a20_line = qemu_allocate_irqs(handle_a20_line_change,
+ x86_env_get_cpu(first_cpu), 2);
i8042 = isa_create_simple(isa_bus, "i8042");
i8042_setup_a20_line(i8042, &a20_line[0]);
if (!no_vmport) {
.driver = "usb-tablet",\
.property = "usb_version",\
.value = stringify(1),\
+ },{\
+ .driver = "virtio-net-pci",\
+ .property = "ctrl_mac_addr",\
+ .value = "off", \
}
static QEMUMachine pc_machine_v1_3 = {
ich9_lpc->ioapic = gsi_state->ioapic_irq;
pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
ICH9_LPC_NB_PIRQS);
+ pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
isa_bus = ich9_lpc->isa_bus;
/*end early*/
#include "qemu/range.h"
#include "xen.h"
#include "pam.h"
+#include "sysemu/sysemu.h"
/*
* I440FX chipset data sheet.
#define XEN_PIIX_NUM_PIRQS 128ULL
#define PIIX_PIRQC 0x60
+/*
+ * Reset Control Register: PCI-accessible ISA-Compatible Register at address
+ * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
+ */
+#define RCR_IOPORT 0xcf9
+
typedef struct PIIX3State {
PCIDevice dev;
/* This member isn't used. Just for save/load compatibility */
int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
+
+ /* Reset Control Register contents */
+ uint8_t rcr;
+
+ /* IO memory region for Reset Control Register (RCR_IOPORT) */
+ MemoryRegion rcr_mem;
} PIIX3State;
struct PCII440FXState {
pci_conf[0xae] = 0x00;
d->pic_levels = 0;
+ d->rcr = 0;
}
static int piix3_post_load(void *opaque, int version_id)
}
}
+static bool piix3_rcr_needed(void *opaque)
+{
+ PIIX3State *piix3 = opaque;
+
+ return (piix3->rcr != 0);
+}
+
+static const VMStateDescription vmstate_piix3_rcr = {
+ .name = "PIIX3/rcr",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT8(rcr, PIIX3State),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static const VMStateDescription vmstate_piix3 = {
.name = "PIIX3",
.version_id = 3,
.minimum_version_id_old = 2,
.post_load = piix3_post_load,
.pre_save = piix3_pre_save,
- .fields = (VMStateField []) {
+ .fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(dev, PIIX3State),
VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
PIIX_NUM_PIRQS, 3),
VMSTATE_END_OF_LIST()
+ },
+ .subsections = (VMStateSubsection[]) {
+ {
+ .vmsd = &vmstate_piix3_rcr,
+ .needed = piix3_rcr_needed,
+ },
+ { 0 }
+ }
+};
+
+
+static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
+{
+ PIIX3State *d = opaque;
+
+ if (val & 4) {
+ qemu_system_reset_request();
+ return;
}
+ d->rcr = val & 2; /* keep System Reset type only */
+}
+
+static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
+{
+ PIIX3State *d = opaque;
+
+ return d->rcr;
+}
+
+static const MemoryRegionOps rcr_ops = {
+ .read = rcr_read,
+ .write = rcr_write,
+ .endianness = DEVICE_LITTLE_ENDIAN
};
static int piix3_initfn(PCIDevice *dev)
PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
isa_bus_new(&d->dev.qdev, pci_address_space_io(dev));
+
+ memory_region_init_io(&d->rcr_mem, &rcr_ops, d, "piix3-reset-control", 1);
+ memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
+ &d->rcr_mem, 1);
+
qemu_register_reset(piix3_reset, d);
return 0;
}
(unsigned long)reg_info.flags);
vdev->config_size = reg_info.size;
+ if (vdev->config_size == PCI_CONFIG_SPACE_SIZE) {
+ vdev->pdev.cap_present &= ~QEMU_PCI_CAP_EXPRESS;
+ }
vdev->config_offset = reg_info.offset;
error:
pdc->exit = vfio_exitfn;
pdc->config_read = vfio_pci_read_config;
pdc->config_write = vfio_pci_write_config;
+ pdc->is_express = 1; /* We might be */
}
static const TypeInfo vfio_pci_dev_info = {
memcpy(&netcfg, config, sizeof(netcfg));
- if (memcmp(netcfg.mac, n->mac, ETH_ALEN)) {
+ if (!(n->vdev.guest_features >> VIRTIO_NET_F_CTRL_MAC_ADDR & 1) &&
+ memcmp(netcfg.mac, n->mac, ETH_ALEN)) {
memcpy(n->mac, netcfg.mac, ETH_ALEN);
qemu_format_nic_info_str(&n->nic->nc, n->mac);
}
n->mac_table.multi_overflow = 0;
n->mac_table.uni_overflow = 0;
memset(n->mac_table.macs, 0, MAC_TABLE_ENTRIES * ETH_ALEN);
+ memcpy(&n->mac[0], &n->nic->conf->macaddr, sizeof(n->mac));
memset(n->vlans, 0, MAX_VLAN >> 3);
}
}
static int virtio_net_handle_rx_mode(VirtIONet *n, uint8_t cmd,
- VirtQueueElement *elem)
+ struct iovec *iov, unsigned int iov_cnt)
{
uint8_t on;
+ size_t s;
- if (elem->out_num != 2 || elem->out_sg[1].iov_len != sizeof(on)) {
- error_report("virtio-net ctrl invalid rx mode command");
- exit(1);
+ s = iov_to_buf(iov, iov_cnt, 0, &on, sizeof(on));
+ if (s != sizeof(on)) {
+ return VIRTIO_NET_ERR;
}
- on = ldub_p(elem->out_sg[1].iov_base);
-
- if (cmd == VIRTIO_NET_CTRL_RX_MODE_PROMISC)
+ if (cmd == VIRTIO_NET_CTRL_RX_PROMISC) {
n->promisc = on;
- else if (cmd == VIRTIO_NET_CTRL_RX_MODE_ALLMULTI)
+ } else if (cmd == VIRTIO_NET_CTRL_RX_ALLMULTI) {
n->allmulti = on;
- else if (cmd == VIRTIO_NET_CTRL_RX_MODE_ALLUNI)
+ } else if (cmd == VIRTIO_NET_CTRL_RX_ALLUNI) {
n->alluni = on;
- else if (cmd == VIRTIO_NET_CTRL_RX_MODE_NOMULTI)
+ } else if (cmd == VIRTIO_NET_CTRL_RX_NOMULTI) {
n->nomulti = on;
- else if (cmd == VIRTIO_NET_CTRL_RX_MODE_NOUNI)
+ } else if (cmd == VIRTIO_NET_CTRL_RX_NOUNI) {
n->nouni = on;
- else if (cmd == VIRTIO_NET_CTRL_RX_MODE_NOBCAST)
+ } else if (cmd == VIRTIO_NET_CTRL_RX_NOBCAST) {
n->nobcast = on;
- else
+ } else {
return VIRTIO_NET_ERR;
+ }
return VIRTIO_NET_OK;
}
static int virtio_net_handle_mac(VirtIONet *n, uint8_t cmd,
- VirtQueueElement *elem)
+ struct iovec *iov, unsigned int iov_cnt)
{
struct virtio_net_ctrl_mac mac_data;
+ size_t s;
- if (cmd != VIRTIO_NET_CTRL_MAC_TABLE_SET || elem->out_num != 3 ||
- elem->out_sg[1].iov_len < sizeof(mac_data) ||
- elem->out_sg[2].iov_len < sizeof(mac_data))
+ if (cmd == VIRTIO_NET_CTRL_MAC_ADDR_SET) {
+ if (iov_size(iov, iov_cnt) != sizeof(n->mac)) {
+ return VIRTIO_NET_ERR;
+ }
+ s = iov_to_buf(iov, iov_cnt, 0, &n->mac, sizeof(n->mac));
+ assert(s == sizeof(n->mac));
+ qemu_format_nic_info_str(&n->nic->nc, n->mac);
+ return VIRTIO_NET_OK;
+ }
+
+ if (cmd != VIRTIO_NET_CTRL_MAC_TABLE_SET) {
return VIRTIO_NET_ERR;
+ }
n->mac_table.in_use = 0;
n->mac_table.first_multi = 0;
n->mac_table.multi_overflow = 0;
memset(n->mac_table.macs, 0, MAC_TABLE_ENTRIES * ETH_ALEN);
- mac_data.entries = ldl_p(elem->out_sg[1].iov_base);
+ s = iov_to_buf(iov, iov_cnt, 0, &mac_data.entries,
+ sizeof(mac_data.entries));
+ mac_data.entries = ldl_p(&mac_data.entries);
+ if (s != sizeof(mac_data.entries)) {
+ return VIRTIO_NET_ERR;
+ }
+ iov_discard_front(&iov, &iov_cnt, s);
- if (sizeof(mac_data.entries) +
- (mac_data.entries * ETH_ALEN) > elem->out_sg[1].iov_len)
+ if (mac_data.entries * ETH_ALEN > iov_size(iov, iov_cnt)) {
return VIRTIO_NET_ERR;
+ }
if (mac_data.entries <= MAC_TABLE_ENTRIES) {
- memcpy(n->mac_table.macs, elem->out_sg[1].iov_base + sizeof(mac_data),
- mac_data.entries * ETH_ALEN);
+ s = iov_to_buf(iov, iov_cnt, 0, n->mac_table.macs,
+ mac_data.entries * ETH_ALEN);
+ if (s != mac_data.entries * ETH_ALEN) {
+ return VIRTIO_NET_ERR;
+ }
n->mac_table.in_use += mac_data.entries;
} else {
n->mac_table.uni_overflow = 1;
}
+ iov_discard_front(&iov, &iov_cnt, mac_data.entries * ETH_ALEN);
+
n->mac_table.first_multi = n->mac_table.in_use;
- mac_data.entries = ldl_p(elem->out_sg[2].iov_base);
+ s = iov_to_buf(iov, iov_cnt, 0, &mac_data.entries,
+ sizeof(mac_data.entries));
+ mac_data.entries = ldl_p(&mac_data.entries);
+ if (s != sizeof(mac_data.entries)) {
+ return VIRTIO_NET_ERR;
+ }
- if (sizeof(mac_data.entries) +
- (mac_data.entries * ETH_ALEN) > elem->out_sg[2].iov_len)
+ iov_discard_front(&iov, &iov_cnt, s);
+
+ if (mac_data.entries * ETH_ALEN != iov_size(iov, iov_cnt)) {
return VIRTIO_NET_ERR;
+ }
- if (mac_data.entries) {
- if (n->mac_table.in_use + mac_data.entries <= MAC_TABLE_ENTRIES) {
- memcpy(n->mac_table.macs + (n->mac_table.in_use * ETH_ALEN),
- elem->out_sg[2].iov_base + sizeof(mac_data),
- mac_data.entries * ETH_ALEN);
- n->mac_table.in_use += mac_data.entries;
- } else {
- n->mac_table.multi_overflow = 1;
+ if (n->mac_table.in_use + mac_data.entries <= MAC_TABLE_ENTRIES) {
+ s = iov_to_buf(iov, iov_cnt, 0, n->mac_table.macs,
+ mac_data.entries * ETH_ALEN);
+ if (s != mac_data.entries * ETH_ALEN) {
+ return VIRTIO_NET_ERR;
}
+ n->mac_table.in_use += mac_data.entries;
+ } else {
+ n->mac_table.multi_overflow = 1;
}
return VIRTIO_NET_OK;
}
static int virtio_net_handle_vlan_table(VirtIONet *n, uint8_t cmd,
- VirtQueueElement *elem)
+ struct iovec *iov, unsigned int iov_cnt)
{
uint16_t vid;
+ size_t s;
- if (elem->out_num != 2 || elem->out_sg[1].iov_len != sizeof(vid)) {
- error_report("virtio-net ctrl invalid vlan command");
+ s = iov_to_buf(iov, iov_cnt, 0, &vid, sizeof(vid));
+ vid = lduw_p(&vid);
+ if (s != sizeof(vid)) {
return VIRTIO_NET_ERR;
}
- vid = lduw_p(elem->out_sg[1].iov_base);
-
if (vid >= MAX_VLAN)
return VIRTIO_NET_ERR;
struct virtio_net_ctrl_hdr ctrl;
virtio_net_ctrl_ack status = VIRTIO_NET_ERR;
VirtQueueElement elem;
+ size_t s;
+ struct iovec *iov;
+ unsigned int iov_cnt;
while (virtqueue_pop(vq, &elem)) {
- if ((elem.in_num < 1) || (elem.out_num < 1)) {
+ if (iov_size(elem.in_sg, elem.in_num) < sizeof(status) ||
+ iov_size(elem.out_sg, elem.out_num) < sizeof(ctrl)) {
error_report("virtio-net ctrl missing headers");
exit(1);
}
- if (elem.out_sg[0].iov_len < sizeof(ctrl) ||
- elem.in_sg[elem.in_num - 1].iov_len < sizeof(status)) {
- error_report("virtio-net ctrl header not in correct element");
- exit(1);
+ iov = elem.out_sg;
+ iov_cnt = elem.out_num;
+ s = iov_to_buf(iov, iov_cnt, 0, &ctrl, sizeof(ctrl));
+ iov_discard_front(&iov, &iov_cnt, sizeof(ctrl));
+ if (s != sizeof(ctrl)) {
+ status = VIRTIO_NET_ERR;
+ } else if (ctrl.class == VIRTIO_NET_CTRL_RX) {
+ status = virtio_net_handle_rx_mode(n, ctrl.cmd, iov, iov_cnt);
+ } else if (ctrl.class == VIRTIO_NET_CTRL_MAC) {
+ status = virtio_net_handle_mac(n, ctrl.cmd, iov, iov_cnt);
+ } else if (ctrl.class == VIRTIO_NET_CTRL_VLAN) {
+ status = virtio_net_handle_vlan_table(n, ctrl.cmd, iov, iov_cnt);
}
- ctrl.class = ldub_p(elem.out_sg[0].iov_base);
- ctrl.cmd = ldub_p(elem.out_sg[0].iov_base + sizeof(ctrl.class));
-
- if (ctrl.class == VIRTIO_NET_CTRL_RX_MODE)
- status = virtio_net_handle_rx_mode(n, ctrl.cmd, &elem);
- else if (ctrl.class == VIRTIO_NET_CTRL_MAC)
- status = virtio_net_handle_mac(n, ctrl.cmd, &elem);
- else if (ctrl.class == VIRTIO_NET_CTRL_VLAN)
- status = virtio_net_handle_vlan_table(n, ctrl.cmd, &elem);
-
- stb_p(elem.in_sg[elem.in_num - 1].iov_base, status);
+ s = iov_from_buf(elem.in_sg, elem.in_num, 0, &status, sizeof(status));
+ assert(s == sizeof(status));
virtqueue_push(vq, &elem, sizeof(status));
virtio_notify(vdev, vq);
#define VIRTIO_NET_F_CTRL_VLAN 19 /* Control channel VLAN filtering */
#define VIRTIO_NET_F_CTRL_RX_EXTRA 20 /* Extra RX mode control support */
+#define VIRTIO_NET_F_CTRL_MAC_ADDR 23 /* Set MAC address */
+
#define VIRTIO_NET_S_LINK_UP 1 /* Link is up */
#define TX_TIMER_INTERVAL 150000 /* 150 us */
* 0 and 1 are supported with the VIRTIO_NET_F_CTRL_RX feature.
* Commands 2-5 are added with VIRTIO_NET_F_CTRL_RX_EXTRA.
*/
-#define VIRTIO_NET_CTRL_RX_MODE 0
- #define VIRTIO_NET_CTRL_RX_MODE_PROMISC 0
- #define VIRTIO_NET_CTRL_RX_MODE_ALLMULTI 1
- #define VIRTIO_NET_CTRL_RX_MODE_ALLUNI 2
- #define VIRTIO_NET_CTRL_RX_MODE_NOMULTI 3
- #define VIRTIO_NET_CTRL_RX_MODE_NOUNI 4
- #define VIRTIO_NET_CTRL_RX_MODE_NOBCAST 5
+#define VIRTIO_NET_CTRL_RX 0
+ #define VIRTIO_NET_CTRL_RX_PROMISC 0
+ #define VIRTIO_NET_CTRL_RX_ALLMULTI 1
+ #define VIRTIO_NET_CTRL_RX_ALLUNI 2
+ #define VIRTIO_NET_CTRL_RX_NOMULTI 3
+ #define VIRTIO_NET_CTRL_RX_NOUNI 4
+ #define VIRTIO_NET_CTRL_RX_NOBCAST 5
/*
- * Control the MAC filter table.
+ * Control the MAC
*
* The MAC filter table is managed by the hypervisor, the guest should
* assume the size is infinite. Filtering should be considered
* first sg list contains unicast addresses, the second is for multicast.
* This functionality is present if the VIRTIO_NET_F_CTRL_RX feature
* is available.
+ *
+ * The ADDR_SET command requests one out scatterlist, it contains a
+ * 6 bytes MAC address. This functionality is present if the
+ * VIRTIO_NET_F_CTRL_MAC_ADDR feature is available.
*/
struct virtio_net_ctrl_mac {
uint32_t entries;
};
#define VIRTIO_NET_CTRL_MAC 1
#define VIRTIO_NET_CTRL_MAC_TABLE_SET 0
+ #define VIRTIO_NET_CTRL_MAC_ADDR_SET 1
/*
* Control VLAN filtering
DEFINE_PROP_BIT("ctrl_vq", _state, _field, VIRTIO_NET_F_CTRL_VQ, true), \
DEFINE_PROP_BIT("ctrl_rx", _state, _field, VIRTIO_NET_F_CTRL_RX, true), \
DEFINE_PROP_BIT("ctrl_vlan", _state, _field, VIRTIO_NET_F_CTRL_VLAN, true), \
- DEFINE_PROP_BIT("ctrl_rx_extra", _state, _field, VIRTIO_NET_F_CTRL_RX_EXTRA, true)
+ DEFINE_PROP_BIT("ctrl_rx_extra", _state, _field, VIRTIO_NET_F_CTRL_RX_EXTRA, true), \
+ DEFINE_PROP_BIT("ctrl_mac_addr", _state, _field, VIRTIO_NET_F_CTRL_MAC_ADDR, true)
#endif
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
-#if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC)
+#if defined(TARGET_SPARC) || defined(TARGET_PPC)
cpu_reset(ENV_GET_CPU(env));
#endif
# Generate timestamp files for .h include files
-%.h: %.h-timestamp
- @test -f $@ || cp $< $@
+config-%.h: config-%.h-timestamp
+ @cmp $< $@ >/dev/null 2>&1 || cp $< $@
-%.h-timestamp: %.mak
- $(call quiet-command, sh $(SRC_PATH)/scripts/create_config < $< > $@, " GEN $(TARGET_DIR)$*.h")
- @cmp $@ $*.h >/dev/null 2>&1 || cp $@ $*.h
+config-%.h-timestamp: config-%.mak
+ $(call quiet-command, sh $(SRC_PATH)/scripts/create_config < $< > $@, " GEN $(TARGET_DIR)config-$*.h")
+
+.PHONY: clean-timestamp
+clean-timestamp:
+ rm -f *.timestamp
+clean: clean-timestamp
# will delete the target of a rule if commands exit with a nonzero exit status
.DELETE_ON_ERROR:
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
int is_write, int mmu_idx);
#define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault
-void cpu_x86_set_a20(CPUX86State *env, int a20_state);
+void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index)
{
/* x86 mmu */
/* XXX: add PGE support */
-void cpu_x86_set_a20(CPUX86State *env, int a20_state)
+void x86_cpu_set_a20(X86CPU *cpu, int a20_state)
{
+ CPUX86State *env = &cpu->env;
+
a20_state = (a20_state != 0);
if (a20_state != ((env->a20_mask >> 20) & 1)) {
#if defined(DEBUG_MMU)
obj-y += m68k-semi.o
obj-y += translate.o op_helper.o helper.o cpu.o
-obj-$(CONFIG_SOFTMMU) += machine.o
#include "cpu.h"
#include "qemu-common.h"
+#include "migration/vmstate.h"
static void m68k_set_feature(CPUM68KState *env, int feature)
static ObjectClass *m68k_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
+ char *typename;
if (cpu_model == NULL) {
return NULL;
}
- oc = object_class_by_name(cpu_model);
+ typename = g_strdup_printf("%s-" TYPE_M68K_CPU, cpu_model);
+ oc = object_class_by_name(typename);
+ g_free(typename);
if (oc != NULL && (object_class_dynamic_cast(oc, TYPE_M68K_CPU) == NULL ||
object_class_is_abstract(oc))) {
return NULL;
cpu_exec_init(env);
}
+static const VMStateDescription vmstate_m68k_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
+
static void m68k_cpu_class_init(ObjectClass *c, void *data)
{
M68kCPUClass *mcc = M68K_CPU_CLASS(c);
CPUClass *cc = CPU_CLASS(c);
+ DeviceClass *dc = DEVICE_CLASS(c);
mcc->parent_reset = cc->reset;
cc->reset = m68k_cpu_reset;
cc->class_by_name = m68k_cpu_class_by_name;
+ dc->vmsd = &vmstate_m68k_cpu;
}
static void register_cpu_type(const M68kCPUInfo *info)
{
TypeInfo type_info = {
- .name = info->name,
.parent = TYPE_M68K_CPU,
.instance_init = info->instance_init,
};
+ type_info.name = g_strdup_printf("%s-" TYPE_M68K_CPU, info->name);
type_register(&type_info);
+ g_free((void *)type_info.name);
}
static const TypeInfo m68k_cpu_type_info = {
name_a = object_class_get_name(class_a);
name_b = object_class_get_name(class_b);
- if (strcmp(name_a, "any") == 0) {
+ if (strcmp(name_a, "any-" TYPE_M68K_CPU) == 0) {
return 1;
- } else if (strcmp(name_b, "any") == 0) {
+ } else if (strcmp(name_b, "any-" TYPE_M68K_CPU) == 0) {
return -1;
} else {
return strcasecmp(name_a, name_b);
{
ObjectClass *c = data;
CPUListState *s = user_data;
+ const char *typename;
+ char *name;
+ typename = object_class_get_name(c);
+ name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_M68K_CPU));
(*s->cpu_fprintf)(s->file, "%s\n",
- object_class_get_name(c));
+ name);
+ g_free(name);
}
void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf)
obj-y += translate.o op_helper.o helper.o cpu.o
-obj-$(CONFIG_SOFTMMU) += mmu.o machine.o
+obj-$(CONFIG_SOFTMMU) += mmu.o
#include "cpu.h"
#include "qemu-common.h"
+#include "migration/vmstate.h"
/* CPUClass::reset() */
set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
}
+static const VMStateDescription vmstate_mb_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
+
static void mb_cpu_class_init(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
mcc->parent_reset = cc->reset;
cc->reset = mb_cpu_reset;
+
+ dc->vmsd = &vmstate_mb_cpu;
}
static const TypeInfo mb_cpu_type_info = {
#define cpu_gen_code cpu_mb_gen_code
#define cpu_signal_handler cpu_mb_signal_handler
-#define CPU_SAVE_VERSION 1
-
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _nommu
#define MMU_MODE1_SUFFIX _kernel
+++ /dev/null
-#include "hw/hw.h"
-#include "hw/boards.h"
-
-void cpu_save(QEMUFile *f, void *opaque)
-{
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- return 0;
-}
static void cpu_register(const OpenRISCCPUInfo *info)
{
TypeInfo type_info = {
- .name = info->name,
.parent = TYPE_OPENRISC_CPU,
.instance_size = sizeof(OpenRISCCPU),
.instance_init = info->initfn,
.class_size = sizeof(OpenRISCCPUClass),
};
+ type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name);
type_register(&type_info);
+ g_free((void *)type_info.name);
}
static const TypeInfo openrisc_cpu_type_info = {
.parent = TYPE_CPU,
.instance_size = sizeof(OpenRISCCPU),
.instance_init = openrisc_cpu_initfn,
- .abstract = false,
+ .abstract = true,
.class_size = sizeof(OpenRISCCPUClass),
.class_init = openrisc_cpu_class_init,
};
name_a = object_class_get_name(class_a);
name_b = object_class_get_name(class_b);
- if (strcmp(name_a, "any") == 0) {
+ if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
return 1;
- } else if (strcmp(name_b, "any") == 0) {
+ } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
return -1;
} else {
return strcmp(name_a, name_b);
{
ObjectClass *oc = data;
CPUListState *s = user_data;
+ const char *typename;
+ char *name;
+ typename = object_class_get_name(oc);
+ name = g_strndup(typename,
+ strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
(*s->cpu_fprintf)(s->file, " %s\n",
- object_class_get_name(oc));
+ name);
+ g_free(name);
}
void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf)
obj-y += translate.o helper.o cpu.o interrupt.o
obj-y += int_helper.o fpu_helper.o cc_helper.o mem_helper.o misc_helper.o
-obj-$(CONFIG_SOFTMMU) += machine.o ioinst.o
+obj-$(CONFIG_SOFTMMU) += ioinst.o
obj-$(CONFIG_KVM) += kvm.o
#include "cpu.h"
#include "qemu-common.h"
#include "qemu/timer.h"
-#ifndef CONFIG_USER_ONLY
#include "hw/hw.h"
+#ifndef CONFIG_USER_ONLY
#include "sysemu/arch_init.h"
#endif
#endif
}
+static const VMStateDescription vmstate_s390_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
+
static void s390_cpu_class_init(ObjectClass *oc, void *data)
{
S390CPUClass *scc = S390_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(scc);
+ DeviceClass *dc = DEVICE_CLASS(oc);
scc->parent_reset = cc->reset;
cc->reset = s390_cpu_reset;
+
+ dc->vmsd = &vmstate_s390_cpu;
}
static const TypeInfo s390_cpu_type_info = {
+++ /dev/null
-/*
- * QEMU S390x machine definitions
- *
- * Copyright (c) 2009 Alexander Graf <agraf@suse.de>
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "hw/hw.h"
-#include "hw/boards.h"
-
-void cpu_save(QEMUFile *f, void *opaque)
-{
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- return 0;
-}
obj-y += translate.o op_helper.o helper.o cpu.o
-obj-$(CONFIG_SOFTMMU) += machine.o
#include "cpu.h"
#include "qemu-common.h"
+#include "migration/vmstate.h"
/* CPUClass::reset() */
env->movcal_backup_tail = &(env->movcal_backup);
}
+static const VMStateDescription vmstate_sh_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
+
static void superh_cpu_class_init(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
scc->parent_reset = cc->reset;
cc->reset = superh_cpu_reset;
+
+ dc->vmsd = &vmstate_sh_cpu;
}
static const TypeInfo superh_cpu_type_info = {
obj-y += translate.o op_helper.o helper.o cpu.o
obj-y += ucf64_helper.o
-obj-$(CONFIG_SOFTMMU) += machine.o softmmu.o
+obj-$(CONFIG_SOFTMMU) += softmmu.o
#include "cpu.h"
#include "qemu-common.h"
+#include "migration/vmstate.h"
static inline void set_feature(CPUUniCore32State *env, int feature)
{
static ObjectClass *uc32_cpu_class_by_name(const char *cpu_model)
{
ObjectClass *oc;
+ char *typename;
if (cpu_model == NULL) {
return NULL;
}
- oc = object_class_by_name(cpu_model);
+ typename = g_strdup_printf("%s-" TYPE_UNICORE32_CPU, cpu_model);
+ oc = object_class_by_name(typename);
+ g_free(typename);
if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_UNICORE32_CPU) ||
object_class_is_abstract(oc))) {
oc = NULL;
CPUUniCore32State *env = &cpu->env;
cpu_exec_init(env);
- env->cpu_model_str = object_get_typename(obj);
#ifdef CONFIG_USER_ONLY
env->uncached_asr = ASR_MODE_USER;
tlb_flush(env, 1);
}
+static const VMStateDescription vmstate_uc32_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
+
static void uc32_cpu_class_init(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
cc->class_by_name = uc32_cpu_class_by_name;
+ dc->vmsd = &vmstate_uc32_cpu;
}
static void uc32_register_cpu_type(const UniCore32CPUInfo *info)
{
TypeInfo type_info = {
- .name = info->name,
.parent = TYPE_UNICORE32_CPU,
.instance_init = info->instance_init,
};
+ type_info.name = g_strdup_printf("%s-" TYPE_UNICORE32_CPU, info->name);
type_register(&type_info);
+ g_free((void *)type_info.name);
}
static const TypeInfo uc32_cpu_type_info = {
int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw,
int mmu_idx);
-#define CPU_SAVE_VERSION 2
-
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
}
cpu = UNICORE32_CPU(object_new(object_class_get_name(oc)));
env = &cpu->env;
+ env->cpu_model_str = cpu_model;
if (inited) {
inited = 0;
+++ /dev/null
-/*
- * Generic machine functions for UniCore32 ISA
- *
- * Copyright (C) 2010-2012 Guan Xuetao
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation, or any later version.
- * See the COPYING file in the top-level directory.
- */
-#include "hw/hw.h"
-
-void cpu_save(QEMUFile *f, void *opaque)
-{
- hw_error("%s not supported yet.\n", __func__);
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- hw_error("%s not supported yet.\n", __func__);
-
- return 0;
-}
obj-y += core-dc233c.o
obj-y += core-fsf.o
obj-y += translate.o op_helper.o helper.o cpu.o
-obj-$(CONFIG_SOFTMMU) += machine.o
#include "cpu.h"
#include "qemu-common.h"
+#include "migration/vmstate.h"
/* CPUClass::reset() */
cpu_exec_init(env);
}
+static const VMStateDescription vmstate_xtensa_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
+
static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
{
+ DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
xcc->parent_reset = cc->reset;
cc->reset = xtensa_cpu_reset;
+
+ dc->vmsd = &vmstate_xtensa_cpu;
}
static const TypeInfo xtensa_cpu_type_info = {
+++ /dev/null
-/*
- * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the Open Source and Linux Lab nor the
- * names of its contributors may be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "hw/hw.h"
-#include "hw/boards.h"
-
-void cpu_save(QEMUFile *f, void *opaque)
-{
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- return 0;
-}
# Auto-generated header for tracing routines
$(obj)/generated-tracers.h: $(obj)/generated-tracers.h-timestamp
+ @cmp -s $< $@ || cp $< $@
$(obj)/generated-tracers.h-timestamp: $(SRC_PATH)/trace-events $(BUILD_DIR)/config-host.mak
$(call quiet-command,$(TRACETOOL) \
--format=h \
--backend=$(TRACE_BACKEND) \
< $< > $@," GEN $(patsubst %-timestamp,%,$@)")
- @cmp -s $@ $(patsubst %-timestamp,%,$@) || cp $@ $(patsubst %-timestamp,%,$@)
######################################################################
# Auto-generated tracing routines (non-DTrace)
ifneq ($(TRACE_BACKEND),dtrace)
$(obj)/generated-tracers.c: $(obj)/generated-tracers.c-timestamp
+ @cmp -s $< $@ || cp $< $@
$(obj)/generated-tracers.c-timestamp: $(SRC_PATH)/trace-events $(BUILD_DIR)/config-host.mak
$(call quiet-command,$(TRACETOOL) \
--format=c \
--backend=$(TRACE_BACKEND) \
< $< > $@," GEN $(patsubst %-timestamp,%,$@)")
- @cmp -s $@ $(patsubst %-timestamp,%,$@) || cp $@ $(patsubst %-timestamp,%,$@)
$(obj)/generated-tracers.o: $(obj)/generated-tracers.c $(obj)/generated-tracers.h
endif
BOOL isTabletEnabled;
}
- (void) resizeContentToWidth:(int)w height:(int)h displayState:(DisplayState *)ds;
+- (void) updateDataOffset:(DisplayState *)ds;
- (void) grabMouse;
- (void) ungrabMouse;
- (void) toggleFullScreen:(id)sender;
[self setFrame:NSMakeRect(cx, cy, cw, ch)];
}
+- (void) updateDataOffset:(DisplayState *)ds
+{
+ COCOA_DEBUG("QemuCocoaView: UpdateDataOffset\n");
+
+ // update screenBuffer
+ if (dataProviderRef) {
+ CGDataProviderRelease(dataProviderRef);
+ }
+
+ size_t size = ds_get_width(ds) * 4 * ds_get_height(ds);
+ dataProviderRef = CGDataProviderCreateWithData(NULL, ds_get_data(ds),
+ size, NULL);
+}
+
- (void) toggleFullScreen:(id)sender
{
COCOA_DEBUG("QemuCocoaView: toggleFullScreen\n");
[sheet close];
- asprintf(&argv[0], "%s", bin);
- asprintf(&argv[1], "-hda");
- asprintf(&argv[2], "%s", img);
+ argv[0] = g_strdup_printf("%s", bin);
+ argv[1] = g_strdup_printf("-hda");
+ argv[2] = g_strdup_printf("%s", img);
printf("Using argc %d argv %s -hda %s\n", 3, bin, img);
vga_hw_update();
}
+static void cocoa_setdata(DisplayState *ds)
+{
+ [cocoaView updateDataOffset:ds];
+}
+
static void cocoa_cleanup(void)
{
COCOA_DEBUG("qemu_cocoa: cocoa_cleanup\n");
dcl->dpy_gfx_update = cocoa_update;
dcl->dpy_gfx_resize = cocoa_resize;
dcl->dpy_refresh = cocoa_refresh;
+ dcl->dpy_gfx_setdata = cocoa_setdata;
register_displaychangelistener(ds, dcl);
projects / sdk / emulator / qemu.git / commitdiff