drm/i915/vrr: Make delayed vblank operational in VRR mode on adl/dg2

On adl/dg2 a chicken bit needs to be set for TRANS_SET_CONTENXT_LATENCY
to take effect in VRR mode. Can't really think of a reason why we'd
ever disable that chicken bit, so let's just always set it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230320203352.19515-4-ville.syrjala@linux.intel.com
Reviewed-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 6d749de..348a7cc 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -173,6 +173,14 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
        struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
        enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
+       /*
+        * TRANS_SET_CONTEXT_LATENCY with VRR enabled
+        * requires this chicken bit on ADL/DG2.
+        */
+       if (DISPLAY_VER(dev_priv) == 13)
+               intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
+                            0, PIPE_VBLANK_WITH_DELAY);
+
        if (!crtc_state->vrr.enable)
                return;
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0e6dfdf..ae387c7 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4560,13 +4560,12 @@
                                            [TRANSCODER_B] = _CHICKEN_TRANS_B, \
                                            [TRANSCODER_C] = _CHICKEN_TRANS_C, \
                                            [TRANSCODER_D] = _CHICKEN_TRANS_D))
-
 #define _MTL_CHICKEN_TRANS_A   0x604e0
 #define _MTL_CHICKEN_TRANS_B   0x614e0
 #define MTL_CHICKEN_TRANS(trans)       _MMIO_TRANS((trans), \
                                                    _MTL_CHICKEN_TRANS_A, \
                                                    _MTL_CHICKEN_TRANS_B)
-
+#define  PIPE_VBLANK_WITH_DELAY                REG_BIT(31) /* ADL/DG2 */
 #define  HSW_FRAME_START_DELAY_MASK    REG_GENMASK(28, 27)
 #define  HSW_FRAME_START_DELAY(x)      REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
 #define  VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */